NEC D30412RJ-75 (VR4400MC)
Information
History
Architecture
Identification
Pinouts
Support chips
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Type
Microprocessor
Introduction date
May 1993
Manufacturing process
2.3 million transistors
Data bus width
64 bit
Package
447-pin staggered ceramic PGA
Speed (MHz)
75 (external)
150 (internal)
Clock multiplier
2, 3, 4, 6 or 8
On-chip peripherals
128-bit secondary cache bus interface
System control processor
Memory management unit
Physical memory (GB)
64
Virtual memory
2 GB (user mode); 2.5 GB (supervisor mode); 4 GB (kernel mode)
Level 1 cache size
16 KB direct-mapped code cache
16 KB direct-mapped data cache
Level 2 cache size
External 128 KB - 4 MB
Floating Point Unit
Integrated
Notes:
Binary compatible with R3000A
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Last modified: 19 Feb 2006
R4400 family
List of processor families
(c) Copyright 2003 Gennadiy Shvets
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R4400 familyList of processor families