| General information |
| Type | CPU / Microprocessor |
| Frequency (MHz) ? | 100 (externla)
200 (internal) |
| Clock multiplier ? | 2, 3, 4, 6 or 8 |
| Package | 447-pin staggered ceramic PGA |
| Introduction date | 05/23/1994 |
| |
| Architecture / Microarchitecture |
| Manufacturing process | 0.35 micron CMOS technology
2.3 million transistors |
| Die size | 184 mm2 |
| Data width | 64 bit |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 16 KB direct-mapped code cache
16 KB direct-mapped data cache |
| Level 2 cache size ? | External 128 KB - 4 MB |
| Physical memory (GB) | 64 |
| Virtual memory | 2 GB (user mode); 2.5 GB (supervisor mode); 4 GB (kernel mode) |
| On-chip peripherals | - 128-bit secondary cache bus interface
- System control processor
- Memory management unit
|
| |
| Electrical/Thermal parameters |
| |
| Notes |
- Binary compatible with R3000A
|
