IDT 79RV5000-180BS272I
Information
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History
Architecture
Identification
Pinouts
Support chips
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Type
Microprocessor
Data bus width
64 bit
Package
272-ball SBGA
Speed (MHz)
180
Bus frequency (MHz)
up to 90
Clock multiplier
from 2 to 8
On-chip peripherals
Secondary cache controller
Level 1 cache size
32 KB 2-way set associative instruction cache
32 KB 2-way set associative data cache
Level 2 cache size
external 512 KB, 1 MB or 2 MB
Floating Point Unit
Integrated
V core (V)
3.3 ± 5%
Min/Max operating temperature (°C)
-40 - 85
Min power dissipation (W)
0.4 (Standby mode)
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Last modified: 2 Dec 2005
R5000 family
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(c) Copyright 2003 Gennadiy Shvets