| General information |
| Type | CPU / Microprocessor |
| Frequency (MHz) ? | 200 |
| Bus speed (MHz) ? | up to 100 |
| Clock multiplier ? | from 2 to 8 |
| Package | 272-ball SBGA |
| Introduction date | 01/08/1996 |
| |
| Architecture / Microarchitecture |
| Data width | 64 bit |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 32 KB 2-way set associative instruction cache
32 KB 2-way set associative data cache |
| Level 2 cache size ? | external 512 KB, 1 MB or 2 MB |
| On-chip peripherals | Secondary cache controller |
| |
| Electrical/Thermal parameters |
| V core (V) ? | 3.3 ± 5% |
| Min/Max operating temperature (°C) ? | 0 - 85 |
| Min/Max power dissipation (W) ? | 0.4 (Standby mode) / 4.5 |
