| Type | Microprocessor |
| Introduction date | 2-Jun-97 |
| Manufacturing process | 0.35 micron 5-layer metal CMOS technology
5.4 million transistors |
| Data bus width | 64 bit |
| Package | 787-land ceramic LGA |
| Speed (MHz) | 300 |
| Bus frequency (MHz) | 75 (4x clock multiplier); 100 (3x clock multiplier) |
| Clock multiplier | 3x or 4x |
| On-chip peripherals |
- Memory Management Unit
- Level 2 cache controller
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| Other features | Visual Instruction Set |
| Level 1 cache size | 16 KB pseudo 2-way set associative code cache
16 KB write-through direct-mapped data cache |
| Level 2 cache size | external 0.5 MB - 16 MB L2 cache |
| Floating Point Unit | Integrated |
| V core (V) | 2.6 |
| V I/O or secondary (V) | 3.3 |
| Max power dissipation (W) | 26 |
Notes:- Pin-compatible with UltraSparc I
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UltraSparcII family