| General information |
| Type | CPU / Microprocessor |
| Clock multiplier ? | - 3x (UPA64S interface)
- 4x (memory interface, typical)
|
| Package | 587-land ceramic LGA |
| |
| Architecture / Microarchitecture |
| Processor core | Sabre |
| Manufacturing process | 0.35 micron 5-layer metal CMOS process |
| Data width | 64 bit |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 16 KB 2-way set associative code cache
16 KB write-through direct-mapped data cache |
| Level 2 cache size ? | external 0.25 MB - 2 MB L2 cache |
| Features | Visual Instruction Set |
| On-chip peripherals | - Memory Controller Unit
- Level 2 cache controller
- PCI bus controller
- I/O memory management unit
|
| |
| Electrical/Thermal parameters |
| Min/Recommended/Max V core (V) | 2.52 / 2.6 / 2.68 |
| V I/O or secondary (V) | 3.3 ± 5% |
| Min/Max operating temperature (°C) ? | 0 - 105 |
| Typical/Max power dissipation (W) | 27.4 / 39.88 |
