|
Intel Xeon 5150 - HH80556KJ0674M (BX805565150A / BX805565150P)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Server |
| Family | Intel Xeon 5100 |
| Model number ? | 5150 |
| CPU part numbers | HH80556KJ0674M is an OEM/tray microprocessor BX805565150A is a boxed microprocessor BX805565150P is a boxed microprocessor |
| Frequency ? | 2667 MHz |
| Bus speed ? | 1333 MHz |
| Clock multiplier ? | 8 |
| Package | 771-land Flip-Chip Land Grid Array (FC-LGA6)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 771 (LGA771) |
| Introduction date | Jun 26, 2006 |
| End-of-Life date | Last order date for embedded processors is January 27, 2012
Last shipment date for embedded processors is July 27, 2012 |
| Price at introduction | $690 |
| | | S-spec numbers |
|
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Platform | Bensley
Cranberry Lake
Glidewell |
| Processor core ? | Woodcrest |
| Core steppings ? | B0 (QLUJ) B1 (QOXM) B2 (QTIM, SL9RU, SLABM) G0 (QXQX, SLAGA) |
| CPUIDs | 6F6 (SL9RU, SLABM) 6FB (QXQX, SLAGA) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| The number of cores | 2 |
| The number of threads | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 32 KB instruction caches
2 x 32 KB data caches |
| Level 2 cache size ? | Shared 4 MB cache |
| Multiprocessing | Up to 2 processors |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- Extended Memory 64 technology (EM64T) ?
- Virtualization technology ?
- Execute disable bit ?
|
| Low power features | - HALT mode
- Extended HALT mode
- Stop Grant mode ?
- Enhanced SpeedStep technology ?
|
| | | Electrical/Thermal parameters |
| V core ? | 1V - 1.5V (Stepping B2)
0.85V - 1.5V (Stepping G0) |
| Minimum/Maximum operating temperature ? | 5°C - 65°C |
| Maximum power dissipation ? | 111.45 Watt
91.5 Watt (sustained) |
| Thermal Design Power ? | 65 Watt |
| |
| Notes on Intel HH80556KJ0674M |
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
- Part BX805565150A includes 3U+ active / 1U passive thermal solution
- Part BX805565150P includes 2U passive thermal solution
|
CPUs, related to Intel Xeon 5150
• Highlighted numbers and features indicate whether specific processor performs better or worse than Xeon 5150
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions
Pictures (2)
|
| Xeon 5150 (SL9RU) |
|
Top view of the Xeon 5150, B2 stepping (SL9RU) |
 |
|
| Xeon 5150 (SLBAS) |
|
Bottom view of the Xeon 5150, B2 stepping (SLBAS) |
 |
|
News
Aug 07, 2011: A few days ago, Intel published Product Change Notifications
(PCN) documents, where it disclosed plans to discontinue several
socket 1156 processors in 2012. Core i5-760, as well as two unlocked
"K" models, Core i5-655K and Core i7-875K, will be available for order
until February 24, 2012. Last week, Intel also announced discontinuation of a large number
of embedded microprocessors.
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Xeon 5150 CPU.
| Manufacturer: | Intel |
| CPU Family: | Xeon |
| Processor Number: | 5150 |
| Frequency: | 2660 MHz |
|
| Part number: | HH80556KJ0674M |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Xeon(R) CPU 5150 @ 2.66GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6F6 |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 6 (06h) |
| TLB/Cache details: | 3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
2 x 32 KB |
2 x 32 KB |
4 MB |
| Associativity: |
8-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Enhanced SpeedStep |
Debug store |
| |
Debugging extensions |
| |
Digital Thermal Sensor capability |
| |
Direct Cache access |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor 2 |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
|
|