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Intel Xeon E3-1280 CM8062307261903 (BX80623E31280)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Server |
| Family | Intel Xeon E3-1200 |
| Model number ? | E3-1280 |
| CPU part numbers | CM8062307261903 is an OEM/tray microprocessor BX80623E31280 is a boxed microprocessor |
| Frequency ? | 3500 MHz |
| Turbo frequency | 3900 MHz (1 core)
3800 MHz (2 cores)
3700 MHz (3 cores)
3600 MHz (4 cores) |
| Bus speed ? | 5 GT/s DMI |
| Clock multiplier ? | 35 |
| Package | 1155-land Flip-Chip Land Grid Array (FCLGA 1155) |
| Socket | Socket 1155 (Socket H2) |
| Size | 1.48" x 1.48" / 3.75cm x 3.75cm |
| Introduction date | Apr 3, 2011 |
| Price at introduction | $612 |
| | | S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q1HY |
SR00R |
| BX80623E31280 | | + |
| CM8062307261903 | + | + |
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Sandy Bridge |
| Platform | Bromolow |
| Processor core ? | Sandy Bridge |
| Core stepping ? | D2 (Q1HY, SR00R) |
| CPUID | 206A7 (SR00R) |
| Manufacturing process | 0.032 micron High-K metal gate process |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 8 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction cache
4 x 32 KB data cache |
| Level 2 cache size ? | 4 x 256 KB |
| Level 3 cache size | 8 MB |
| Physical memory | 32 GB |
| Multiprocessing | Uniprocessor |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- SSE4.2 ?
- AES instructions
- Advanced Vector Extensions
- Extended Memory 64 technology (EM64T) ?
- Execute disable bit ?
- Virtualization technology (VT-x / VT-d)
- Turbo Boost technology 2.0
- Trusted Execution technology
- HyperThreading technology ?
|
| Low power features | - C1, C3 and C6 thread states
- C1/C1E, C3 and C6 core states
- C1/C1E, C3 and C6 package states
- Enhanced SpeedStep technology ?
|
| On-chip peripherals | - Dual-channel DDR3 memory controller
- Direct Media Interface 2.0
- PCI Express 2.0 interface
|
| | | Electrical/Thermal parameters |
| Minimum/Maximum operating temperature ? | 5°C - 73.6°C |
| Minimum power dissipation | 5.5 Watt (C6 state) |
| Thermal Design Power ? | 95 Watt |
| |
| Notes on Intel CM8062307261903 |
- Memory controller supports DDR3-1066 and DDR3-1333 memory
- ECC memory is supported
|
CPUs, related to Intel Xeon E3-1280
| Model |
Cores / Threads |
Freq. |
Turbo freq. |
L3 cache |
TDP |
Features |
| Intel Xeon E3-1200 family, Socket 1155 |
| Intel Xeon E3-1225 | 4 / 4 | 3.1 GHz | 3.4 GHz | 6 MB | 95 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1220 | 4 / 4 | 3.1 GHz | 3.4 GHz | 8 MB | 80 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1260L | 4 / 8 | 2.4 GHz | 3.3 GHz | 8 MB | 45 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1230 | 4 / 8 | 3.2 GHz | 3.6 GHz | 8 MB | 80 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1235 | 4 / 8 | 3.2 GHz | 3.6 GHz | 8 MB | 95 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1240 | 4 / 8 | 3.3 GHz | 3.7 GHz | 8 MB | 80 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1245 | 4 / 8 | 3.3 GHz | 3.7 GHz | 8 MB | 95 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1270 | 4 / 8 | 3.4 GHz | 3.8 GHz | 8 MB | 80 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1275 | 4 / 8 | 3.4 GHz | 3.8 GHz | 8 MB | 95 Watt | AES, AVX, HT, TXT, TBT |
| Intel Xeon E3-1290 | 4 / 8 | 3.6 GHz | 4 GHz | 8 MB | 95 Watt | AES, AVX, HT, TXT, TBT |
| Other families, Sandy Bridge micro-architecture, Socket 1155 |
| Intel Pentium 350 | 2 / 4 | 1.2 GHz | | 3 MB | 15 Watt | AES, AVX, HT, TXT, TBT |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Xeon E3-1280
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
AES - AES instructions AVX - AVX instructions HT - Hyper-Threading TXT - Trusted Execution TBT - Dynamic Acceleration / Turbo Boost
News
Apr 03, 2011: Intel Xeon E3-1200 server processors for single-CPU workstations
and entry-level servers were added today to official Intel price-list.
This update confirms earlier reports
of the Xeon E3 family launch, planned for the next week. The first
details of the Intel E3-1200 microprocessors emerged last October,
and, as we can tell from the brief specs in the price list, they
stayed without changes. Xeon E3 launch date, though, was delayed by a
few weeks due to a SATA ports defect, discovered in January in Series
6 "Cougar Point" chipsets.
Mar 24, 2011: On March 22 Dell announced PowerEdge C5000 generation of
servers, that combine energy efficiency with high-density form factor.
New products pack up to 12 nodes, or "micro-servers", in a 3U chassis,
and each node can be used as a dedicated server for lightweight
web-based applications. Dedicated systems of these type don't require
large amounts of memory, and can be powered by single CPU. Dell plans
to offer two separate micro-server models - C5125, based on AMD low-
and mid-power microprocessors, and C5220, that uses low- and standard
voltage CPUs from forthcoming Xeon E3-1200 family.
Feb 07, 2011: If you followed recent Intel announcements, you know that Intel is
planning to release large number of mid-class desktop and mobile
dual-core microprocessors this February. Based on information from
Intel ARK database, the launch date was set to February 20. Recent
discovery of a problem with Serial ATA 3 Gb/s ports in the Cougar
Point chipsets may delay the launch, but we don't have a definitive
information regarding this matter. We do have information on hand that
on February 20 Intel also planned to introduce 12 models from Xeon E3
microprocessor series, and three C200-series chipsets: C202, C204 and
C206.
Jan 18, 2011: Yesterday Intel posted Material declaration data sheets for
upcoming Xeon E3-1200 series microprocessors. As a part of these
declarations, they exposed box part numbers and S-Spec numbers of
standard-power Xeon CPUs. The published information confirmed model numbers of
E3-1200-series processors, that were revealed for the first
time in October of last year.
Nov 01, 2010: Earlier this month, we published specifications of upcoming Xeon
E3-1200 series microprocessors. At the time, we knew that Xeons will
be paired with Intel C206 chipset, but didn't have any details of it.
Recently, we learned that the Xeon E3-1200 CPUs will be supported not
by one, but by three slightly different chipsets - C202, C204 and
C206, and we also found their partial specifications.
Oct 06, 2010: Earlier today we revealed Intel's plans to release new version of
Xeon microprocessor for single-socket workstations. The W3690 is not
the only one-way Xeon that we can expect at the beginning of 2011.
In the first quarter Intel is going to replace most of Xeon
3400-series CPUs with new E3-1200 series, based on Sandy Bridge
microarchitecture. Intel Xeon E3-1200 lineup consists of 11 low- and
standard-power microprocessors with core frequencies ranging from 2.2
GHz to 3.5 GHz.
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Xeon E3-1280 CPU.
| Manufacturer: | Intel |
| CPU Family: | Xeon |
| Processor Number: | E3-1280 |
| Frequency: | 3492 MHz |
|
| Part number: | CM8062307261903 |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | jänis |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Xeon(R) CPU E31280 @ 3.50GHz |
| Cores: | 4 |
| Logical processors: | 8 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 206A7 |
| Family: | 6 (06h) |
| Model: | 42 (02Ah) |
| Stepping: | 7 (07h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
L2 TLB: 1-MB, 4-way set associative, 64-byte line size
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
L3 |
| Size: |
4 x 32 KB |
4 x 32 KB |
4 x 256 KB |
8 MB |
| Associativity: |
8-way set associative |
8-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| SSE4.2 |
PCLMULDQ |
| AES instructions |
POPCNT |
| AVX instructions |
SYSENTER/SYSEXIT |
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XSAVE/XRESTORE states |
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XSETBV/XGETBV are enabled |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| Hyper-Threading Technology |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Intel Trusted Execution technology |
Debug store |
| Turbo Boost |
Debugging extensions |
| Enhanced SpeedStep |
Digital Thermal Sensor capability |
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Extended xAPIC support |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Power Limit Notification capability |
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Process context identifiers |
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RDTSCP |
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Self-snoop |
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TSC rate is ensured to be invariant across all states |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Timestamp counter deadline |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
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