Intel Xeon E5-2418L - CM8062000911406


Specifications

General information
TypeCPU / Microprocessor
Market segmentServer
FamilyIntel Xeon E5-2400
Model number  ? E5-2418L
CPU part numberCM8062000911406 is an OEM/tray microprocessor
Frequency  ? 2000 MHz
Turbo frequency2100 MHz
Bus speed  ? 3200 MHz QPI
Package1356-land Flip-Chip Land Grid Array
SocketSocket 1356 (LGA1356)
Size1.77" x 1.67" / 4.5cm x 4.25cm
Introduction dateMay 14, 2012
Price at introduction$387
 
Architecture / Microarchitecture
MicroarchitectureSandy Bridge
PlatformRomley-EN
Processor core  ? Sandy Bridge-EN
Manufacturing process0.032 micron Hi-K metal gate process
Data width64 bit
The number of cores4
The number of threads8
Floating Point UnitIntegrated
Level 3 cache size10 MB
MultiprocessingUp to 2 processors
Features
  • MMX instruction set
  • SSE
  • SSE2
  • SSE3
  • Supplemental SSE3
  • SSE4.1  ? 
  • SSE4.2  ? 
  • AES instructions
  • Advanced Vector Extensions
  • EM64T technology  ? 
  • Execute Disable bit  ? 
  • Hyper-Threading technology  ? 
  • Virtualization technology (VT-x / VT-d)
  • Turbo Boost technology 2.0
  • Trusted Execution Technology
Low power featuresEnhanced SpeedStep technology  ? 
On-chip peripherals
  • 3-channel DDR3 memory controller
  • Direct Media Interface
  • Quick Path Interconnect (1 link)
  • PCI Express 3.0 interface
 
Electrical/Thermal parameters
Thermal Design Power  ? 50 Watt
 
Notes on Intel CM8062000911406
  • Embedded microprocessor
  • Memory controller supports DDR3-1333 memory
  • ECC memory is supported

Pictures (0)

News


Nov 09, 2011: Next year, Intel plans to launch new Xeon E5 group of families for socket 2011 and socket 1356 Romley platforms. There will be three different subfamilies, aimed at single-, dual- and quad-processor servers, based on socket 2011 platform. Only one subfamily, E5-2400, will be compatible with socket B2 (socket 1356). Microprocessors from Xeon E5-2400 series will be built on Sandy Bridge-EN core, and have from 4 to 8 cores, and from 10 MB to 20 MB of L3 cache. They will support three memory channels, incorporate one QPI link, and work in two-way systems.


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