Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Server |
| Family | Intel Xeon 3200 |
| Model number ? | X3210 |
| CPU part numbers | HH80562QH0468M is an OEM/tray microprocessor BX80562X3210 is a boxed microprocessor |
| Frequency ? | 2133 MHz |
| Bus speed ? | 1066 MHz |
| Clock multiplier ? | 8 |
| Package | 775-land Flip-Chip Land Grid Array (FC-LGA6)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 (LGA775) |
| |
| S-spec numbers |
| |
Production processors |
| Part number |
SL9UQ |
SLACU |
| BX80562X3210 | + | + |
| HH80562QH0468M | + | + |
|
| |
| Architecture / Microarchitecture |
| Microarchitecture | Core |
| Platform | Garlow
Kaylo |
| Processor core ? | Kentsfield |
| Core steppings ? | B3 (SL9UQ) G0 (SLACU) |
| CPUIDs | 6F7 (SL9UQ) 6FB (SLACU) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 4 MB shared 8-way associative caches |
| Multiprocessing | Uniprocessor |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- Extended Memory 64 technology (EM64T) ?
- Virtualization technology ?
- Execute disable bit ?
|
| Low power features | - HALT state
- Extended HALT state
- Stop Grant state ?
- Enhanced SpeedStep technology ?
|
| |
| Electrical/Thermal parameters |
| V core ? | 0.85V - 1.5V |
| Minimum/Maximum operating temperature ? | 5°C - 62.2°C (CPUID 06F7h)
85°C (CPUID 06FBh) |
| Maximum power dissipation ? | 164.07 Watt |
| Thermal Design Power ? | 105 Watt (CPUID 06F7h)
100 Watt (CPUID 06FBh) |
| |
| Notes on Intel HH80562QH0468M |
- Bus frequency is 266 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1066 MHz
|
CPUs, related to Intel Xeon X3210
• Highlighted numbers and features indicate whether specific processor performs better or worse than Xeon X3210
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions
TXT - Trusted Execution
CPU ID (2)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Xeon X3210 CPU.
| Manufacturer: | Intel |
| CPU Family: | Xeon |
| Processor Number: | X3210 |
| Frequency: | 2133 MHz |
|
| Part number: | HH80562QH0468M |
| S-Spec Number: | SLACU |
| Comment: | |
| Submitted by: | Stratmaster |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Xeon(R) CPU X3210 @ 2.13GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6FB |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 11 (0Bh) |
| TLB/Cache details: | 3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
32 KB |
32 KB |
4 MB |
| Associativity: |
8-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Enhanced SpeedStep |
Debug store |
| |
Debugging extensions |
| |
Digital Thermal Sensor capability |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor 2 |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
Our CPUID database has 2 records for this microprocessor. See all submitted records.