Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Server |
| Family | Intel Xeon 3300 |
| Model number ? | X3360 |
| CPU part numbers | EU80569KJ073N is an OEM/tray microprocessor BX80569X3360 is a boxed microprocessor |
| Frequency ? | 2833 MHz |
| Bus speed ? | 1333 MHz |
| Clock multiplier ? | 8.5 |
| Package | 775-land Flip-Chip Land Grid Array (FC-LGA8)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 (LGA775) |
| Introduction date | Jan 7, 2008 |
| |
| S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q9TQ |
SLAN5 |
SLAWZ |
SLB8X |
| BX80569X3360 | | | + | + |
| EU80569KJ073N | + | + | + | |
|
| |
| Architecture / Microarchitecture |
| Microarchitecture | Core |
| Platform | Garlow |
| Processor core ? | Yorkfield |
| Core steppings ? | C0 (Q9TQ, SLAN5) C1 (SLAWZ) E0 (SLB8X) |
| CPUIDs | 10676 (SLAN5, SLAWZ) 1067A (SLB8X) |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 6 MB shared 8-way associative caches |
| Multiprocessing | Uniprocessor |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- Extended Memory 64 technology (EM64T) ?
- Virtualization technology ?
- Execute disable bit ?
|
| Low power features | - HALT state
- Extended HALT state
- Stop Grant state ?
- Enhanced SpeedStep technology ?
|
| |
| Electrical/Thermal parameters |
| V core ? | 0.85V - 1.3625V |
| Minimum/Maximum operating temperature ? | 5°C - 71.4°C |
| Minimum/Maximum power dissipation ? | 12 Watt (Extended HALT state) / 131.54 Watt |
| Thermal Design Power ? | 95 Watt |
| |
| Notes on Intel EU80569KJ073N |
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
|
CPUs, related to Intel Xeon X3360
• Highlighted numbers and features indicate whether specific processor performs better or worse than Xeon X3360
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions
TXT - Trusted Execution
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Xeon X3360 CPU.
| Manufacturer: | Intel |
| CPU Family: | Xeon |
| Processor Number: | X3360 |
| Frequency: | 2833 MHz |
|
| Part number: | EU80569KJ073N |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | Andreas Hofer |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Xeon(R) CPU X3360 @ 2.83GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10677 |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 7 (07h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
4 x 32 KB |
4 x 32 KB |
2 x 6 MB |
| Associativity: |
8-way set associative |
8-way set associative |
24-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
|
|
1 cache per 2 cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Intel Trusted Execution technology |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
| |
Digital Thermal Sensor capability |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor 2 |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |