Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Server |
| Family | Intel Xeon 3400 |
| Model number ? | X3440 |
| CPU part numbers | BV80605002517AQ is an OEM/tray microprocessor BX80605X3440 is a boxed microprocessor |
| Frequency ? | 2533 MHz |
| Turbo frequency | 2933 MHz (1 core)
2800 MHz (2 cores)
2667 MHz (3 or 4 cores) |
| Bus speed ? | 2.5 GT/s DMI |
| Clock multiplier ? | 19 |
| Package | 1156-land Flip-Chip Land Grid Array (FC-LGA8)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 1156 (LGA1156) |
| Introduction date | Sep 8, 2009 |
| Price at introduction | $215 |
| |
| S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q3AS |
SLBLF |
| BV80605002517AQ | + | + |
| BX80605X3440 | | + |
|
| |
| Architecture / Microarchitecture |
| Microarchitecture | Nehalem |
| Platform | Foxhollow-WS |
| Processor core ? | Lynnfield |
| Core stepping ? | B1 (SLBLF) |
| CPUID | 106E5 (SLBLF) |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 8 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 4 x 256 KB |
| Level 3 cache size | 8 MB |
| Multiprocessing | Uniprocessor |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- SSE4.2 ?
- EM64T technology ?
- Virtualization technology (VT-x and VT-d)
- Execute Disable bit ?
- Turbo Boost Technology ?
- Trusted Execution Technology
- Hyper-Threading technology ?
|
| Low power features | - Thread C1/C1E, C3 and C6 states
- Core C1/C1E, C3 and C6 states
- Package C1/C1E, C3 and C6 states
- Enhanced SpeedStep technology ?
|
| On-chip peripherals | - Integrated 2-channel DDR3 SDRAM Memory controller
- Direct Media Interface
- PCI Express interface
|
| |
| Electrical/Thermal parameters |
| V core ? | 0.65V - 1.4V |
| Maximum power dissipation ? | 189.78 Watt (peak)
160.08 Watt (sustained) |
| Thermal Design Power ? | 95 Watt |
| |
| Notes on Intel BV80605002517AQ |
- Memory controller supports DDR3-800, DDR3-1066 and DDR3-1333 memory
|
CPUs, related to Intel Xeon X3440
• Highlighted numbers and features indicate whether specific processor performs better or worse than Xeon X3440
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• Features abbreviations:
HT - Hyper-Threading
TBT - Dynamic Acceleration / Turbo Boost
CPU ID (2)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Intel Xeon 2.53 GHz CPU.
| Manufacturer: | Intel |
| CPU Family: | Intel Xeon |
| Processor Number: | 2.53 GHz |
| Frequency: | 2533 MHz |
|
| Part number: | BV80605002517AQ |
| S-Spec Number: | SLBLF |
| Comment: | A+ |
| Submitted by: | MSTTjio |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Xeon(R) CPU X3440 @ 2.53GHz |
| Cores: | 4 |
| Logical processors: | 8 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 106E5 |
| Family: | 6 (06h) |
| Model: | 30 (01Eh) |
| Stepping: | 5 (05h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
L3 |
| Size: |
4 x 32 KB |
4 x 32 KB |
4 x 256 KB |
8 MB |
| Associativity: |
8-way set associative |
4-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
|
|
|
Shared between all cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| SSE4.2 |
POPCNT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Hyper-Threading Technology |
CPL qualified debug store |
| Intel Virtualization |
Debug store |
| Intel Trusted Execution technology |
Debugging extensions |
| Turbo Boost |
Digital Thermal Sensor capability |
| Enhanced SpeedStep |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
RDTSCP |
| |
Self-snoop |
| |
TSC rate is ensured to be invariant across all states |
| |
Thermal monitor |
| |
Thermal monitor 2 |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
Our CPUID database has 2 records for this microprocessor. See all submitted records.