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Intel Xeon X5355 - HH80563KJ0678M (BX80563X5355A / BX80563X5355P)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Server |
| Family | Intel Xeon 5300 |
| Model number ? | X5355 |
| CPU part numbers | HH80563KJ0678M is an OEM/tray microprocessor BX80563X5355A is a boxed microprocessor BX80563X5355P is a boxed microprocessor |
| Frequency ? | 2667 MHz |
| Bus speed ? | 1333 MHz |
| Clock multiplier ? | 8 |
| Package | 771-land Flip-Chip Land Grid Array (FC-LGA6)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 771 (LGA771) |
| Introduction date | Nov 14, 2006 |
| End-of-Life date | Last order date for embedded processors is January 27, 2012
Last shipment date for embedded processors is July 27, 2012 |
| Price at introduction | $1172 |
| | | S-spec numbers |
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| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Platform | Bensley
Glidewell |
| Processor core ? | Clovertown |
| Core steppings ? | B3 (QVQF, SL9YM, SLAC4) G0 (QWTM, SLAEG) |
| CPUIDs | 6F7 (SL9YM, SLAC4) 6FB (QWTM, SLAEG) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 4 MB shared caches |
| Multiprocessing | Up to 2 processors |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- EM64T technology ?
- Execute disable bit ?
- Virtualization technology ?
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| Low power features | - HALT mode
- Extended HALT mode
- Stop Grant mode ?
- Enhanced SpeedStep technology ?
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| | | Electrical/Thermal parameters |
| V core ? | 1V - 1.5V |
| Minimum/Typical/Maximum power dissipation | 5 Watt / 63 Watt / 177.24 Watt
5 Watt / 70 Watt / 159.06 Watt (sustained) |
| Thermal Design Power ? | 120 Watt |
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| Notes on Intel HH80563KJ0678M |
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
- Part BX80563X5355A includes 3U+ active / 1U passive thermal solution
- Part BX80563X5355P includes 2U passive thermal solution
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CPUs, related to Intel Xeon X5355
• Highlighted numbers and features indicate whether specific processor performs better or worse than Xeon X5355
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions
News
Aug 07, 2011: A few days ago, Intel published Product Change Notifications
(PCN) documents, where it disclosed plans to discontinue several
socket 1156 processors in 2012. Core i5-760, as well as two unlocked
"K" models, Core i5-655K and Core i7-875K, will be available for order
until February 24, 2012. Last week, Intel also announced discontinuation of a large number
of embedded microprocessors.
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Xeon X5355 CPU.
| Manufacturer: | Intel |
| CPU Family: | Xeon |
| Processor Number: | X5355 |
| Frequency: | 2660 MHz |
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| Part number: | HH80563KJ0678M |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | Daniel Beer |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Xeon(R) CPU X5355 @ 2.66GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6F7 |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 7 (07h) |
| TLB/Cache details: | 3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
4 x 32 KB |
4 x 32 KB |
2 x 4 MB |
| Associativity: |
8-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Enhanced SpeedStep |
Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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Direct Cache access |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
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