HyperTransport technology

HyperTransport (HT) technology consists of one or more point-to-point high-speed (HyperTransport) links between the CPU and peripheral devices, or between the CPU and other microprocessors in multi-processing systems. Each HyperTransport link consists of 2 unidirectional 16-bit buses, which allow the link to send and receive data simultaneously. The links utilize HyperTransport interface, formerly known as Lightning Data Transport (LDT) interface, hence the names "HyperTransport link" and "HyperTransport technology". The HyperTransport links are independent from each other and from memory interface. Not sharing I/O bandwidth with memory interface is one of the advantages of HyperTransport technology over Front Side Bus interface. Other advantages of the HyperTransport technology are lower latency and better scalability in multi-processor systems.

There are three major versions of HyperTransport interface:

  • HyperTransport 1.x has maximum clock speed 800 MHz. This HT version was implemented in socket 754 microprocessors.
  • HyperTransport 2.0 has maximum clock speed 1.4 GHz. This HT version was implemented in socket 939 and socket AM2 microprocessors. Note: While the HT 2.0 interface supports clocks speeds up to 1.4 GHz, the HT interface in most socket 939 and socket AM2 microprocessors was clocked at 1 GHz.
  • HyperTransport 3.0 has maximum clock speed 2.6 GHz. In addition to faster clock speeds and increased bandwidth, this version of HT includes other features, such as HT link splitting. HT 3.0 was implemented in socket AM2+ microprocessors.

Note: This article applies only to HyperTransport implementation in AMD microprocessors.

Last modified: 15 Oct 2013
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