CPUID information (beta)
|
|
| Part number: | |
| S-Spec Number: | SR07S |
| Comment: | |
| Submitted by: | CPU-World |
| Submitted on: | 2011-11-12 23:58:08 |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Pentium(R) CPU B940 @ 2.00GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 206A7 |
| Family: | 6 (06h) |
| Model: | 42 (02Ah) |
| Stepping: | 7 (07h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L2 TLB: 1-MB, 4-way set associative, 64-byte line size
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
L3 |
| Size: |
2 x 32 KB |
2 x 32 KB |
2 x 256 KB |
2 MB |
| Associativity: |
8-way set associative |
8-way set associative |
8-way set associative |
8-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
Direct-mapped |
Direct-mapped |
Non-inclusive Direct-mapped |
Inclusive Shared between all cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| SSE4.2 |
PCLMULDQ |
| |
POPCNT |
| |
RDTSCP |
| |
SYSENTER/SYSEXIT |
| |
XSAVE / XRESTORE states |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Enhanced SpeedStep |
CPL qualified debug store |
| |
Debug store |
| |
Debugging extensions |
| |
Digital Thermal Sensor capability |
| |
Extended xAPIC support |
| |
LAHF / SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Power Limit Notification capability |
| |
Process context identifiers |
| |
Self-snoop |
| |
TSC rate is ensured to be invariant across all states |
| |
Thermal monitor |
| |
Thermal monitor 2 |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Timestamp counter deadline |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
See raw CPUID data
|
|