| |
| Instruction set extensions | Additional instructions |
|---|
| MMX |
Advanced Bit manipulation |
| AMD extensions to MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4A |
MONITOR/MWAIT |
| SSE4.1 |
PCLMULDQ |
| SSE4.2 |
POPCNT |
| AES |
PREFETCH/PREFETCHW |
| AVX |
RDTSCP |
| FMA4 |
SKINIT / STGI support |
| XOP |
SYSCALL/SYSRET |
| |
SYSENTER/SYSEXIT |
| |
XSAVE / XRESTORE states |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
1 GB large page support |
| 64-bit / Intel 64 |
100MHz multiplier control |
| NX bit/XD-bit |
128-bit SSE instructions |
| Secure Virtual Machine (Virtualization) |
36-bit page-size extensions |
| Turbo Core |
Advanced programmable interrupt controller |
| PowerNow! / Cool'n'Quiet |
Core multi-processing legacy mode |
| |
Debugging extensions |
| |
Extended APIC space |
| |
Hardware P-state control |
| |
Hardware thermal control |
| |
Instruction based sampling |
| |
LAHF / SAHF support in 64-bit mode |
| |
LBR virtualization |
| |
LOCK MOV CR0 means MOV CR8 |
| |
Lightweight profiling support |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Misaligned SSE mode |
| |
Model-specific registers |
| |
Nested page tables |
| |
OS visible workaround |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
SVM lock |
| |
Support for NRIP save |
| |
THERMTRIP |
| |
TSC rate is ensured to be invariant across all states |
| |
Temperature sensor |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
Watchdog timer support |
