Intel Unveils Next Generation HPC Co-Processor

On November 15, Intel unveiled it new Knights Corner co-processors, the first commercial co-processor capable of performing over 1 TFLOPS of double precision floating performance. Based on Intel Many Integrated Core (MIC) technology, this represent a step forward in Intel's goal of developing exascale level performance by 2018. It is also billed as Intel's first commercial MIC architecture product.

Based on technology developed for Intel's now defunct Larrabee graphics processor, Knights corner features 50 x86 maths co-processor cores. It is manufactured using their new 3-D Tri-Gate 22nm process, as used for the upcoming Ivy Bridge core. This makes it ideal for running current x86 software capable of running highly parallel workloads, such as weather modeling, protein folding and other large scientific projects, several of which were demonstrated at SC11. It will be packaged in a standard dual-width 16x PCI-E card, making it an easy upgrade for any system that needs the extra processor power.

"Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel® Pentium Pro® Processors in 1997 as part of Sandia Lab’s ASCI RED system," said Rajeeb Hazra, General Manager of Intel's Technical Computing Group. "Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history."

Intel MIC architecture, with it's x86 core and ability to run existing software, will make it possible to rewrite applications with much more ease than other platforms that would require proprietary programming languages. This makes Knights Corner an ideal platform for rapid deployment of new HPC solutions.

Intel are also working alongside NVidia and the Barcelona Supercomputing Center (BSC) to create an Exascale Laboratory in Barcelona. This is Intel's fourth exascale R&D lab in Europe, and will focus on scalability exascale supercomputer programming and runtime environments.