Features of AMD Piledriver processors
A few days ago AMD posted new technical document, titled Software Optimization Guide for AMD Family 15h Processors (PDF file). Although the guide is intended for developers, it includes some useful information about AMD Family 15h, i.e. Bulldozer. The document not only describes features of current Bulldozer processors, which have model numbers 00h - 0fh (0xh), but also refers to two future generations with model numbers 10h - 1fh (1xh), and 20h - 2fh (2xh). We believe that microprocessors with 10h and higher model numbers will be based on Piledriver cores.
The optimization guide is quite large. References to different features are scattered across the document, so we did our best to find all relevant information. There will be some features, applicable to both 1xh and 2xh CPUs, such as support for 16-bit floating point numbers, and addition of VCVTPH2PS and VCVTPS2PH instructions, used to convert to and from new 16-bit floating-point type. The processors will also incorporate FMA3, Bit Manipulation Instructions (BMI) and Trailing Bit Manipulation instructions, or TBM. In addition to this, there will be some other improvements, such as increased depth of FP load queue, and larger size of level 1 data TLB. Also, latencies of some instructions were reduced.
Microprocessors with model 1xh will have up to 2 modules, or 4 cores, and will lack L3 cache. These characteristics match upcoming Trinity core, that will be utilized by mobile AMD chips. Model 1xh CPUs will also have enhanced IOMMU, or IOMMU v2, that will improve access of I/O devices to system memory, and will add such features as direct access to user I/O space, and interrupt remapping and filtering.
Processors with model number 2xh will have up to 5 modules, or up 10 cores, and support quad-channel DDR3 memory. Like Bulldozer CPUs, which are aimed at both desktop and server markets, 2xh may also target both markets. We suspect that 2xh parts will be released as "Vishera" CPUs on desktop, and "Terramar" and "Sepang" processors for servers. It is possible that server Terramar Opterons, that will integrate two dies on a chip and have up to 20 cores, will support 8 memory channels.
The optimization guide also mentions model 30h - 3fh, and 40h - 4fh processors, however it doesn't contain any details on these chips. The summary of all features, referenced by the optimization guide, is provided below:
Related News (newer articles):
Jan 14, 2012: AMD Trinity to be available mid-2012
Related News (older articles):
Dec 02, 2011: AMD Trinity Production To Commence In March 2012
Nov 07, 2011: More details on Trinity core leaked