First details of Haswell-EP processors emerge

Last week a "bigpao007" user posted several slides in Chiphell forum, detailing features of upcoming Haswell-EP and Haswell-EN server microprocessors. As can be guessed from the name, new chips will be built on Haswell microarchitecture, and accommodate a number of technologies, specific to server market. According to the slides, future 22nm Xeons will integrate 10 or more CPU cores, and 2.5 MB of last level cache per each core. The slides state that the maximum size of the last level cache for the package is 35 MB, which means that the CPU may have up to 14 cores. The Haswell-EP processors will also incorporate quad-channel DDR4 memory controller, supporting transfer speeds 1333, 1600, 1866 and 2133 MT/s. Other on-chip interfaces include 2 QPI channels, and PCI Express 3.0 with 40 lanes on Haswell-EP, and 24 lanes on Haswell-EN. Like current generation of EP/EN Xeons, the future parts will support Hyper-Threading and Turbo Boost technologies. New features on Haswell-EP server microprocessors are integrated voltage regulator, and AVX 2.0 instructions, also called Haswell New Instructions (HNI). Power-saving technologies will be expanded with Per-Core P-State, Uncore Frequency Scaling and Energy-Efficient Turbo features.

The leaked slides also provide high-level information on a C610 chipset, codenamed "Wellsburg", that will be paired with Haswell-EP CPUs. The chipset will support 10 SATA 6 GB/s ports, PCI Express 2.0, 8 USB 2 ports, and up to 6 USB 3.0 ports. The C610 will be produced in a 25mm x 25mm package, and will have close to 7 Watt Thermal Design Power under full load. As expected, the chipset will come with an abundance of enterprise features, including Rapid Storage Technology Enterprise with RAID support and optional SSD caching, Intel Node Manager 3.0 and vPRO/AMT firmware options, support for MCTP protocol and end points, SPI enhancements, just to name a few.

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