Recent leak of Intel server roadmap revealed full lineup of E3-1200 v3 microprocessors. While the roadmap didn't have information on Xeon E5 v2 and E7 v2 SKUs, it listed some of their general features. Many of these features were rumored or reported before, nevertheless it is always useful to have confirmed information, coming directly from Intel.
Xeon E7 v2 and "Brickland" platform will be released in Q4 2013. These CPUs will incorporate up to 15 cores and up to 37.5 MB of L3 cache. The CPUs will have Hyper-threading technology enabled, as a result they will be able to execute up to 30 threads at once. The CPUs will also support VT-x, VT-d and VT-c virtualization, Turbo Boost 2.0, Trusted Execution technology, along with Intel Secure Key and OS Guard features. The processors will be coupled with C602J chipset, and will utilize up to four C102/C104 scalable memory buffers per socket. Each scalable memory buffer will support up to 3 DDR3-1600 DIMMS, as such the maximum number of DIMMS per processor is going to be 24. Other communications interfaces on Xeon E7 v2 chips will include 3 QPI links, and up to 32 lanes of PCI Express 3.0.
Xeon E5-2600 v2 series is coming a quarter earlier than the Xeon E7 v2. The CPUs will have up to 12 cores (24 threads), and they are going to support Intel Secure Key and OS Guard features. The maximum size of L3 cache on these Xeons will be 30 MB. On-chip interfaces will include 2 QPI, up to 40 lanes of PCI Express 3.0, and 4 DDR3 memory channels, that will work with DDR3-1866 memory. Xeon E5-1600 v2 series, which will be available at the same time as the E5-2600 v2, will have up to 6 cores, and run up to 12 threads at once.
Xeon E5-2400 processors for socket LGA1356 will have up to 10 cores, and execute up to 20 threads simultaneously. Preliminary launch date of the Xeon E5-2400 v2 series is Q1 2014.
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