SL2S5 (Intel Pentium II 333 MHz)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Pentium II |
| Part number | 80523PX333512 |
| Frequency (MHz) | 333 |
| Bus speed (MHz) ? | 66 |
| Package type | SECC 3.00 |
| Socket type | Slot 1 |
| |
| Architecture / Microarchitecture / Other |
| CPUID | 0651h |
| Core stepping | dA1 |
| Next stepping | Q436 |
| Next production stepping | SL2TV |
| Processor core | Deschutes |
| Manufacturing technology (micron) | 0.25 |
| L2 cache size (KB) ? | 512 |
| Core voltage (V) ? | 2.0 (1.93 - 2.1) |
| Case temperature (°C) ? | 5 - 65 |
| TagRAM | T6P-e |
| TagRAM stepping | A0 |
| Processor substrate revision | B1 |
| |
| Notes on sSpec SL2S5 |
- Cacheable address space supports up to 4 Gbytes.
- L2 cache supports ECC.
|
| |
CPU ID (1)
| Intel Pentium II 333 SL2S5 |
|---|
| Part number: | 80523PX333512 |
| Frequency: | 334 MHz |
|
| Comment: | Deschutes dA1 |
| Submitted by: | Neon |
|
| |
| General information |
|---|
| Vendor: | GenuineIntel |
| Processor type: | Original OEM Processor |
| CPUID signature: | 651 |
| Family: | 6 (06h) |
| Model: | 5 (05h) |
| Stepping: | 1 (01h) |
| TLB/Cache details: | Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Data TLB: 4-MB Pages, 4-way set associative, 8 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries
Instruction TLB: 4-MB Pages, fully associative, 2 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
|---|
| Size: |
16 KB |
16 KB |
512 KB |
| Associativity: |
4-way set
associative |
4-way set
associative |
4-way set
associative |
| Line size: |
32 bytes |
32 bytes |
32 bytes |
| |
| Instruction set extensions | Additional instructions |
|---|
| MMX |
CMOV |
| |
CMPXCHG8B |
| |
FXSAVE/FXRSTORE |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
36-bit page-size extensions |
| |
Debugging extensions |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
