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SL6FK (Intel Mobile Pentium 4-M 2 GHz)

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SL6FK specifications

General information
TypeCPU / Microprocessor
FamilyIntel Mobile Pentium 4-M
Part numberBXM80532GC2000D
RH80532GC041512
Frequency (GHz)  ? 2
Frequency in LFM mode (GHz)1.2
Bus speed (MHz)  ? 400
Package type478-pin FC-PGA
Socket typeSocket 478 (mPGA478B)
 
Architecture / Microarchitecture / Other
CPUID0F27h
Core steppingC1
Qualification sampleQRR1
Previous steppingSL6CL
Next steppingQVR8
Next production steppingSL6V9
Processor coreNorthwood
Manufacturing technology (micron)0.13
L2 cache size (KB)  ? 512
Core voltage (V)  ? 1.3 / 1.2
Case temperature (°C)  ? 100
 
Notes on sSpec SL6FK
  • The first number in the Processor speed and Core voltage fields is for maximum performance mode, the second number is for battery optimized mode.
  • The parts are available starting from September 20, 2002

Related S-Spec numbers

In addition to the SL6FK S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec BXM80532GC2000D RH80532GC041512
B0 QOP1   +
SL6DF +  
B0-Shrink SL6CL + +
C1 QRR1   +
SL6FK + +
D1 QVR8   +
SL6V9 + +

NOTE: Engineering and qualifications samples are marked with this color


SL6FK CPUID information

Intel Mobile Pentium 4-M 2.00 GHz SL6FK
Part number:RH80532GC041512
Frequency:
Comment:
Submitted by:cocoe
 
General information
Vendor:GenuineIntel
Processor name (BIOS): Mobile Intel(R) Pentium(R) 4 - M CPU 2.00GHz
Logical processors:1
Processor type:Original OEM Processor
CPUID signature:F27
Family:15 (0Fh)
Model: 2 (02h)
Stepping: 7 (07h)
TLB/Cache details:Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

Cache: L1 data L1 instruction L2
Size: 8 KB 12K uops 512 KB
Associativity: 4-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes   64 bytes
Comments: sectored cache   sectored cache
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG8B
  FXSAVE/FXRSTORE
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
  Debug store
  Debugging extensions
  L1 context ID
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

 

2006-07-02 18:56:27
Posted by: Stratmaster

Additional Picture

2012-02-29 16:09:28
Posted by: Josh

Top of chip, high-resolution.

Additional Picture

Additional Picture

2012-02-29 16:10:11
Posted by: Josh

Bottom of chip, high-resolution.

Additional Picture

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