SL6V7 (Intel Mobile Pentium 4-M 1.8 GHz)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Mobile Pentium 4-M |
| Part number | BXM80532GC1800D
RH80532GC033512 |
| Frequency (GHz) | 1.8 |
| Frequency in LFM mode (GHz) | 1.2 |
| Bus speed (MHz) ? | 400 |
| Package type | 478-pin FC-PGA |
| Socket type | Socket 478 (mPGA478B) |
| |
| Architecture / Microarchitecture / Other |
| CPUID | 0F29h |
| Core stepping | D1 |
| Qualification sample | QVS4 |
| Previous stepping | SL6FH |
| Processor core | Northwood |
| Manufacturing technology (micron) | 0.13 |
| L2 cache size (KB) ? | 512 |
| Core voltage (V) ? | 1.3 / 1.2 |
| Case temperature (°C) ? | 100 |
| |
| Notes on sSpec SL6V7 |
- The first number in the Processor speed and Core voltage fields is for maximum performance mode, the second number is for battery optimized mode.
- The parts are available starting from Jun 2, 2003
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CPU ID (1)
| Intel Mobile Intel Pentium 4 - M 1.80 GHz SL6V7 |
|---|
| Part number: | RH80532GC033512 |
| Frequency: | |
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| Comment: | |
| Submitted by: | cocoe |
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| General information |
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| Vendor: | GenuineIntel |
| Processor name (BIOS): | Mobile Intel(R) Pentium(R) 4 - M CPU 1.80GHz |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F29 |
| Family: | 15 (0Fh) |
| Model: | 2 (02h) |
| Stepping: | 9 (09h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: |
L1 data |
L1 instruction |
L2 |
|---|
| Size: |
8 KB |
12K uops |
512 KB |
| Associativity: |
4-way set
associative |
8-way set
associative |
8-way set
associative |
| Line size: |
64 bytes |
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64 bytes |
| Comments: |
sectored cache |
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sectored cache |
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| Instruction set extensions | Additional instructions |
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| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG8B |
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FXSAVE/FXRSTORE |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
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| On-chip Floating Point Unit |
36-bit page-size extensions |
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Debug store |
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Debugging extensions |
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L1 context ID |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
