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SL7J7 (Intel Pentium 4 540)

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SL7J7 specifications

General information
TypeCPU / Microprocessor
FamilyIntel Pentium 4
Processor number  ? 540
Part numberBX80547PG3200E
JM80547PG0881M
Processor markings3.20GHZ/1M/800
Frequency (GHz)  ? 3.2
Bus speed (MHz)  ? 800
Clock multiplier  ? 16
Package type775-land FC-LGA4
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID0F34h
Core steppingD0
Next steppingQ98X
Next production steppingSL7PW
Processor corePrescott
Manufacturing technology (micron)0.09
L2 cache size (MB)  ? 1
FeaturesHyper-Threading technology
Core voltage (V)  ? 1.4
Case temperature (°C)  ? 67.7
 
Notes on sSpec SL7J7
  • Microprocessors with this S-Spec have multiple VIDs.
  • This S-spec supports the 775_VR_CONFIG_04A (mainstream) guidelines for processors with Iccmax up to 78A, and VID up to 1.4V.

Related S-Spec numbers

In addition to the SL7J7 S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec B80547PG0881M HH80547PG0881M JM80547PG0881M BX80547PG3200E BX80547PG3200EJ BX80547PG3200EM
D0 Q01M     +      
Q02M     +      
SL7J7     + +    
SL7KL +     +    
SL7LA     +     +
D0? QS16     +      
E0 Q98X     +      
Q99X     +      
SL7PW     +   +  
SL7PX     +      
SL82Z +          
SL832     +      
Unknown SL8BY     +      

NOTE: Engineering and qualifications samples are marked with this color


SL7J7 CPUID information

Intel Pentium 4 540 SL7J7
Part number:JM80547PG0881M
Frequency:3200 MHz
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS): Intel(R) Pentium(R) 4 CPU 3.20GHz
Cores:1
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:F34
Family:15 (0Fh)
Model: 3 (03h)
Stepping: 4 (04h)
TLB/Cache details:Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

Cache: L1 data L1 instruction L2
Size: 16 KB 12K uops 1 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes   64 bytes
Comments: Direct-mapped   Non-inclusive
Direct-mapped
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG8B
SSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
Hyper-Threading Technology 64-bit debug store
  Advanced programmable interrupt controller
  CPL qualified debug store
  Debug store
  Debugging extensions
  L1 context ID
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

Pentium 4 540 SL7J7

2008-11-12 21:52:58
Posted by: gshv

Pentium 4 540 SL7J7

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2012-01-24 10:57:07
Posted by: Didz

Front Image

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2012-01-24 10:58:22
Posted by: Didz

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