CPU ID (2)
| Intel Pentium 4 520J SL7PR |
|---|
| Part number: | JM80547PG0721M |
| Frequency: | 2992 MHz |
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| Comment: | |
| Submitted by: | cocoe |
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| General information |
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| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Pentium(R) 4 CPU 2.80GHz |
| Cores: | 1 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F41 |
| Family: | 15 (0Fh) |
| Model: | 4 (04h) |
| Stepping: | 1 (01h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: |
L1 data |
L1 instruction |
L2 |
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| Size: |
16 KB |
12K uops |
1 MB |
| Associativity: |
8-way set
associative |
8-way set
associative |
8-way set
associative |
| Line size: |
64 bytes |
|
64 bytes |
| Comments: |
sectored cache |
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sectored cache |
| |
| Instruction set extensions | Additional instructions |
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| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG8B |
| SSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
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| On-chip Floating Point Unit |
36-bit page-size extensions |
| NX bit/XD-bit |
64-bit debug store |
| Hyper-Threading Technology |
Advanced programmable interrupt controller |
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CPL qualified debug store |
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Debug store |
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Debugging extensions |
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L1 context ID |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
Our CPUID database has 2 records for this microprocessor. See all submitted records.
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