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SL8CP (Intel Pentium D 820)

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SL8CP specifications

General information
TypeCPU / Microprocessor
FamilyIntel Pentium D
Processor number  ? 820
Part numberHH80551PG0722MN
BX80551PG2800FN
BX80551PG2800FT
Frequency (GHz)  ? 2.8
Bus speed (MHz)  ? 800
Clock multiplier  ? 14
Package type775-land FC-LGA4
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID0F47h
Core steppingB0
Qualification sampleQEKC
Previous steppingSL88T
Processor coreSmithfield
Manufacturing technology (micron)0.09
Number of cores2
L2 cache size (MB)  ? 2
FeaturesEM64T technology  ? 
Execute disable bit  ? 
Core voltage (V)  ? 1.25 - 1.4
Case temperature (°C)  ? 64.1
 
Notes on sSpec SL8CP
  • This part also ships as a boxed processor with an unattached fan heatsink.
  • The processor does not support Hyper-Threading technology.
  • This part does not support Enhanced SpeedStep technology.
  • The parts are available starting from October 21, 2005

Related S-Spec numbers

In addition to the SL8CP S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec HH80551PG0722MN BX80551PG2800FN BX80551PG2800FT
A0 SL88T + + +
B0 QEKC +    
SL8CP + + +

NOTE: Engineering and qualifications samples are marked with this color


SL8CP CPUID information

Intel Pentium D 820 SL8CP
Part number:HH80551PG0722MN
Frequency:
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS): Intel(R) Pentium(R) D CPU 2.80GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:F47
Family:15 (0Fh)
Model: 4 (04h)
Stepping: 7 (07h)
TLB/Cache details:Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

Cache: L1 data L1 instruction L2
Size: 16 KB 12K uops 1 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes   64 bytes
Comments: sectored cache   sectored cache
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
  FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
  CPL qualified debug store
  Debug store
  Debugging extensions
  L1 context ID
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

 

2012-06-13 12:36:29
Posted by: Homosapien

 

2012-06-13 12:37:00
Posted by: Homosapien

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