SL8S2 (Intel Celeron D 310)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Celeron D |
| Processor number ? | 310 |
| Part number | NE80546RE046256
BX80546RE2130C |
| Frequency (GHz) | 2.133 |
| Bus speed (MHz) ? | 533 |
| Clock multiplier ? | 16 |
| Package type | 478-pin FC-mPGA4 |
| Socket type | Socket 478 (mPGA478B) |
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| Architecture / Microarchitecture / Other |
| CPUID | 0F49h |
| Core stepping | G1 |
| Manufacturing technology (micron) | 0.09 |
| L2 cache size (KB) ? | 256 |
| Core voltage (V) ? | 1.25 - 1.4 |
| Case temperature (°C) ? | 67 |
| Package revision | 01 |
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| Notes on sSpec SL8S2 |
- This part also ships as a boxed processor with an unattached fan heatsink.
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CPU ID (1)
| Intel Celeron D 2.13 GHz SL8S2 |
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| Part number: | RK80546RE046256 |
| Frequency: | |
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| Comment: | |
| Submitted by: | cocoe |
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| General information |
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| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) CPU 2.13GHz |
| Cores: | 1 |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F49 |
| Family: | 15 (0Fh) |
| Model: | 4 (04h) |
| Stepping: | 9 (09h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: |
L1 data |
L1 instruction |
L2 |
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| Size: |
16 KB |
12K uops |
256 KB |
| Associativity: |
8-way set
associative |
8-way set
associative |
4-way set
associative |
| Line size: |
64 bytes |
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64 bytes |
| Comments: |
sectored cache |
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sectored cache |
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| Instruction set extensions | Additional instructions |
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| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG8B |
| SSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
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| On-chip Floating Point Unit |
36-bit page-size extensions |
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64-bit debug store |
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Advanced programmable interrupt controller |
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CPL qualified debug store |
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Debug store |
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Debugging extensions |
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L1 context ID |
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LAHF / SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
