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SL96P (Intel Celeron D 352)
Specifications
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Celeron D |
| Processor number ? | 352 |
| Part number | HH80552RE088512 BX80552352 |
| Frequency (GHz) | 3.2 |
| Bus speed (MHz) ? | 533 |
| Clock multiplier ? | 24 |
| Package type | 775-land FC-LGA4 |
| Socket type | Socket 775 (LGA775) |
| Architecture / Microarchitecture / Other | |
| CPUID | 0F64h |
| Core stepping | C1 |
| Manufacturing technology (micron) | 0.065 |
| L2 cache size (KB) ? | 512 |
| Features | EM64T technology ? Execute disable bit ? |
| Core voltage (V) ? | 1.25 - 1.3 |
| Case temperature (°C) ? | 69.2 |
There are no notes on sSpec SL96P | |
CPU ID (2)
| Intel Celeron D 352 SL96P | |||||||||
|---|---|---|---|---|---|---|---|---|---|
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| ||||||||
| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) D CPU 3.20GHz |
| Cores: | 1 |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F64 |
| Family: | 15 (0Fh) |
| Model: | 6 (06h) |
| Stepping: | 4 (04h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 16 KB | 12K uops | 512 KB |
| Associativity: | 8-way set associative |
8-way set associative |
8-way set associative |
| Line size: | 64 bytes | 64 bytes | |
| Comments: | sectored cache | sectored cache |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG16B | ||
| SSE3 | CMPXCHG8B | ||
| FXSAVE/FXRSTORE | |||
| MONITOR/MWAIT | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit / Intel 64 | 64-bit debug store | ||
| NX bit/XD-bit | Advanced programmable interrupt controller | ||
| CPL qualified debug store | |||
| Debug store | |||
| Debugging extensions | |||
| L1 context ID | |||
| LAHF/SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
Our CPUID database has 2 records for this microprocessor. See all submitted records.
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Find Celeron D S-Spec numbers with:
SL96P
batch L608B392
2v under LN2
7286.49 MHz