SL9KM (Intel Celeron D 352)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Celeron D |
| Processor number ? | 352 |
| Part number | BX80552352
HH80552RE088512 |
| Frequency (GHz) | 3.2 |
| Bus speed (MHz) ? | 533 |
| Clock multiplier ? | 24 |
| Package type | 775-land FC-LGA4 |
| Socket type | Socket 775 (LGA775) |
| |
| Architecture / Microarchitecture / Other |
| CPUID | 0F65h |
| Core stepping | D0 |
| Manufacturing technology (micron) | 0.065 |
| L2 cache size (KB) ? | 512 |
| Features | EM64T technology ?
Execute disable bit ? |
| Core voltage (V) ? | 1.25 - 1.3 |
| Case temperature (°C) ? | 64.4 |
| Thermal Design Power (Watt) ? | 65 |
| |
| Notes on sSpec SL9KM |
- Boxed parts are available starting from Dec 8, 2006
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CPU ID (1)
| Intel Celeron D 352 SL9KM |
|---|
| Part number: | HH80552RE088512 |
| Frequency: | 3191 MHz |
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| Comment: | |
| Submitted by: | cocoe |
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| General information |
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| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) D CPU 3.20GHz |
| Cores: | 1 |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F65 |
| Family: | 15 (0Fh) |
| Model: | 6 (06h) |
| Stepping: | 5 (05h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: |
L1 data |
L1 instruction |
L2 |
|---|
| Size: |
16 KB |
12K uops |
512 KB |
| Associativity: |
8-way set
associative |
8-way set
associative |
8-way set
associative |
| Line size: |
64 bytes |
|
64 bytes |
| Comments: |
sectored cache |
|
sectored cache |
| |
| Instruction set extensions | Additional instructions |
|---|
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
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FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
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| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
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CPL qualified debug store |
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Debug store |
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Debugging extensions |
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L1 context ID |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
