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SL9S5 (Intel Core 2 Extreme X6800)

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SL9S5 specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core 2 Extreme
Processor number  ? X6800
Part numberHH80557PH0774M
BX80557X6800
Processor markings2.93GHz/4M/1066/05B
Frequency (GHz)  ? 2.933
Bus speed (MHz)  ? 1066
Clock multiplier  ? 11
Package type775-land FC-LGA6
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID06F6h
Core steppingB2
Processor coreConroe XE
Manufacturing technology (micron)0.065
Number of cores2
L2 cache size (MB)  ? 4
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Thermal Monitor 2
Virtualization technology
Core voltage (V)  ? 0.85 - 1.3625
Case temperature (°C)  ? 60.4
Thermal Design Power (Watt)  ? 75
 
Notes on sSpec SL9S5
  • The processor supports the 775_VR_CONFIG_05B (performance) guidelines for processors with TDP up to 130 Watt, Iccmax up to 125A, and VID up to 1.4V.

Related S-Spec numbers

In addition to the SL9S5 S-Spec, this processor was also manufactured with two pre-production S-Spec numbers:

SteppingS-Spec HH80557PH0774M BX80557X6800
B1 QPHV +  
B2 QTOI +  
SL9S5 + +

NOTE: Engineering and qualifications samples are marked with this color


SL9S5 CPUID information

Intel Core 2 Extreme X6800 SL9S5
Part number:HH80557PH0774M
Frequency:2040 MHz
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM)2 CPU X6800 @ 2.93GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:6F6
Family: 6 (06h)
Model:15 (0Fh)
Stepping: 6 (06h)
TLB/Cache details:3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 32 KB 32 KB 4 MB
Associativity: 8-way set
associative
8-way set
associative
16-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

Our CPUID database has 2 records for this microprocessor. See all submitted records.

Comments

Intel X6800 SL9S5 Extreme

2009-04-24 17:40:24
Posted by: Osmin

Intel X6800 SL9S5 Extreme

X6800-SL9S5

2010-01-13 06:07:00
Posted by: ZZZ1ZZ

X6800-SL9S5

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