Search CPU-World

Search site contents:

SL9S9 (Intel Core 2 Duo E6400)

Identify another S-Spec code, or another CPU:

The specs can be used for short-term listings on auction and classifieds sites:

Get HTML and forum link code in case if you want to link to this page:

Search S-Specs

Find Core 2 Duo S-Spec numbers with:

Same socket
Same CPUID
Same stepping

SL9S9 specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core 2 Duo
Processor number  ? E6400
Part numberHH80557PH0462M
BX80557E6400
Processor markings2.13GHZ/2M/1066/06
Frequency (GHz)  ? 2.133
Bus speed (MHz)  ? 1066
Clock multiplier  ? 8
Package type775-land FC-LGA6
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID06F6h
Core steppingB2
Next steppingQUHB
Next production steppingSL9T9
Processor coreConroe
Manufacturing technology (micron)0.065
Number of cores2
L2 cache size (MB)  ? 2
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Thermal Monitor 2
Virtualization technology
Core voltage (V)  ? 0.85 - 1.3625
Case temperature (°C)  ? 61.4
Thermal Design Power (Watt)  ? 65
 
Notes on sSpec SL9S9
  • The processor supports the 775_VR_CONFIG_06 guidelines for processors with TDP up to 65 Watt, and Iccmax up to 75A.

Related S-Spec numbers

In addition to the SL9S9 S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec HH80557PH0462M BX80557E6400
A1 QJZO +  
B1 QPGY +  
B2 QTNO +  
SL9S9 + +
L2 QUHB +  
SL9T9 + +
M0 SLA97 +  
Unknown QWJQ +  
SLA5D +  

NOTE: Engineering and qualifications samples are marked with this color


SL9S9 CPUID information

Intel Core 2 Duo E6400 SL9S9
Part number:HH80557PH0462M
Frequency:2133 MHz
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM)2 CPU 6400 @ 2.13GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:6F6
Family: 6 (06h)
Model:15 (0Fh)
Stepping: 6 (06h)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 2 x 32 KB 2 x 32 KB 2 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
Intel Virtualization Advanced programmable interrupt controller
Enhanced SpeedStep CPL qualified debug store
  Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

Terms and Conditions · Privacy Policy · Contact Us (c) Copyright 2003 - 2010 Gennadiy Shvets