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SLA2E (Intel Celeron M 550)
Specifications
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Celeron M |
| Processor number ? | 550 |
| Part number | LF80537NE0411M BX80537550 |
| Frequency (MHz) | 2000 |
| Bus speed (MHz) ? | 533 |
| Clock multiplier ? | 15 |
| Package type | 478-pin Micro-FCPGA |
| Socket type | Socket P |
| Architecture / Microarchitecture / Other | |
| CPUID | 10661h |
| Core stepping | A1 |
| Manufacturing technology (micron) | 0.065 |
| L2 cache size (KB) ? | 1024 |
| Features | EM64T technology ? Execute disable bit ? |
| Core voltage (V) ? | 0.95 - 1.3 |
| Case temperature (°C) ? | 100 |
| Thermal Design Power (Watt) ? | 27 |
| Notes on sSpec SLA2E | |
| |
CPU ID (1)
| Intel Celeron M 550 SLA2E | |||||||||
|---|---|---|---|---|---|---|---|---|---|
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| ||||||||
| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) CPU 550 @ 2.00GHz |
| Cores: | 1 |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10661 |
| Family: | 6 (06h) |
| Model: | 22 (016h) |
| Stepping: | 1 (01h) |
| TLB/Cache details: | 64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 32 KB | 32 KB | 1 MB |
| Associativity: | 8-way set associative |
8-way set associative |
4-way set associative |
| Line size: | 64 bytes | 64 bytes | 64 bytes |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG16B | ||
| SSE3 | CMPXCHG8B | ||
| SSSE3 | FXSAVE/FXRSTORE | ||
| MONITOR/MWAIT | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit / Intel 64 | 64-bit debug store | ||
| NX bit/XD-bit | Advanced programmable interrupt controller | ||
| CPL qualified debug store | |||
| Debug store | |||
| Debugging extensions | |||
| Digital Thermal Sensor capability | |||
| LAHF/SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor 2 | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
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