SLA8Z (Intel Pentium Dual-Core E2160)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Pentium Dual-Core |
| Processor number ? | E2160 |
| Part number | HH80557PG0331M BX80557E2160 BXC80557E2160 |
| Processor markings | 1.80GHZ/1M/800/06 |
| Frequency (GHz) | 1.8 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 9 |
| Package type | 775-land FC-LGA6 |
| Socket type | Socket 775 (LGA775) |
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| Architecture / Microarchitecture / Other |
| CPUID | 06FDh |
| Core stepping | M0 |
| Qualification sample | QYRG |
| Previous stepping | SLA3H |
| Processor core | Allendale |
| Manufacturing technology (micron) | 0.065 |
| Number of cores | 2 |
| L2 cache size (KB) ? | 1024 |
| Features | EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Extended Halt state Extended Stop Grant state Thermal Monitor 2 |
| Core voltage (V) ? | 1.162 - 1.312 |
| Case temperature (°C) ? | 73.2 |
| Thermal Design Power (Watt) ? | 65 |
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| Notes on sSpec SLA8Z |
- The parts are available starting from Jul 23, 2007
- Changes in M0 stepping: Maximum case temperature will change to 73.2°C, The CPU will return brand string "Intel(R) Pentium(R) Dual CPU, Different position and the number of capacitors on the back of the CPU.
- Boxed part is discontinued. Last order date for is May 15, 2009. Last shipment date for is August 14, 2009.
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CPU ID (1)
| Intel Pentium Dual-Core E2160 SLA8Z |
| Part number: | HH80557PG0331M |
| Frequency: | |
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| Comment: | |
| Submitted by: | CPU-World |
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| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Pentium(R) Dual CPU E2160 @ 1.80GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6FD |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 13 (0Dh) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
32 KB |
32 KB |
1 MB |
| Associativity: |
8-way set associative |
8-way set associative |
4-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
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| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Enhanced SpeedStep |
CPL qualified debug store |
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Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |