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SLA9U (Intel Core 2 Duo E6850)

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SLA9U specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core 2 Duo
Processor number  ? E6850
Part numberHH80557PJ0804MG
Processor markings3.00GHZ/4M/1333/06
Frequency (GHz)  ? 3
Bus speed (MHz)  ? 1333
Clock multiplier  ? 9
Package type775-land FC-LGA6
Socket typeSocket 775 (LGA775)
Architecture / Microarchitecture / Other
Core steppingG0
Manufacturing technology (micron)0.065
Number of cores2
L2 cache size (MB)  ? 4
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Extended Stop Grant state
Thermal Monitor 2
Trusted Execution technology
Virtualization technology
Core voltage (V)  ? 0.962 - 1.35
Case temperature (°C)  ? 72
Thermal Design Power (Watt)  ? 65
Notes on sSpec SLA9U
  • The processor supports the 775_VR_CONFIG_06 guidelines for processors with TDP up to 65 Watt, and Iccmax up to 75A.
  • The part is discontinued. Last order date for OEM and boxed processors is March 6, 2009. Last shipment date for boxed processors is June 5, 2009. Last shipment date for OEM processors is May 7, 2010.

Related S-Spec numbers

In addition to the SLA9U S-Spec, this processor was also manufactured with two pre-production S-Spec numbers:

SteppingS-Spec HH80557PJ0804MG BX80557E6850
E0 QSCU +  
G0 QXHK +  
SLA9U + +

NOTE: Engineering and qualifications samples are marked with this color

SLA9U CPUID information

Intel Core 2 Duo E6850 SLA9U
Part number:HH80557PJ0804MG
Frequency:2999 MHz
Submitted by:CPU-World
General information
Processor name (BIOS):Intel(R) Core(TM)2 Duo CPU E6850 @ 3.00GHz
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:6FB
Family: 6 (06h)
Model:15 (0Fh)
Stepping:11 (0Bh)
TLB/Cache details:3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 32 KB 32 KB 4 MB
Associativity: 8-way set
8-way set
16-way set
Line size: 64 bytes 64 bytes 64 bytes
Instruction set extensionsAdditional instructions
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
Intel Virtualization Advanced programmable interrupt controller
Intel Trusted Execution technology CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

Core 2 Duo e6850

2009-11-09 19:45:06
Posted by: VistaViewer

Core 2 Duo e6850


2011-03-13 09:20:37
Posted by: pineapple face

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