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SLALK (Intel Core 2 Duo T5270)

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SLALK specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core 2 Duo Mobile
Processor number  ? T5270
Part numberLF80537GG0172M
Frequency (GHz)  ? 1.4
Bus speed (MHz)  ? 800
Clock multiplier  ? 7
Package type478-pin micro-FCPGA
 
Architecture / Microarchitecture / Other
CPUID06FDh
Core steppingM0
Processor coreMerom
Manufacturing technology (micron)0.065
Number of cores2
L2 cache size (MB)  ? 2
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Core voltage (V)  ? 1.075 - 1.175
Case temperature (°C)  ? 100
Thermal Design Power (Watt)  ? 35
 
There are no notes on sSpec SLALK

Related S-Spec numbers

In addition to the SLALK S-Spec, this processor was also manufactured with one pre-production S-Spec number:

SteppingS-Spec LF80537GG0172M
M0 Q4TG +
SLALK +

NOTE: Engineering and qualifications samples are marked with this color


SLALK CPUID information

Intel Core 2 Duo Mobile T5270 SLALK
Part number:LF80537GG0172M
Frequency:1396 MHz
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM)2 Duo CPU T5270 @ 1.40GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:6FD
Family: 6 (06h)
Model:15 (0Fh)
Stepping:13 (0Dh)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 32 KB 32 KB 2 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Enhanced SpeedStep CPL qualified debug store
  Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
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