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SLAMD (Intel Core 2 Duo Mobile T7300)
Specifications
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Core 2 Duo Mobile |
| Processor number ? | T7300 |
| Part number | LF80537GG0414M |
| Frequency (GHz) | 2 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 10 |
| Package type | 478-pin micro-FCPGA |
| Socket type | Socket P |
| Architecture / Microarchitecture / Other | |
| CPUID | 06FAh |
| Core stepping | G0 |
| Manufacturing technology (micron) | 0.065 |
| Number of cores | 2 |
| L2 cache size (MB) ? | 4 |
| Notes on sSpec SLAMD | |
| |
CPU ID (1)
| Intel Core 2 Duo Mobile T7300 SLAMD | |||||||||
|---|---|---|---|---|---|---|---|---|---|
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| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Duo CPU T7300 @ 2.00GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6FB |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 11 (0Bh) |
| TLB/Cache details: | 3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size 64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 32 KB | 32 KB | 4 MB |
| Associativity: | 8-way set associative |
8-way set associative |
16-way set associative |
| Line size: | 64 bytes | 64 bytes | 64 bytes |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG16B | ||
| SSE3 | CMPXCHG8B | ||
| SSSE3 | FXSAVE/FXRSTORE | ||
| MONITOR/MWAIT | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit / Intel 64 | 64-bit debug store | ||
| NX bit/XD-bit | Advanced programmable interrupt controller | ||
| Intel Virtualization | CPL qualified debug store | ||
| Turbo Boost | Debug store | ||
| Enhanced SpeedStep | Debugging extensions | ||
| Digital Thermal Sensor capability | |||
| LAHF/SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor 2 | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
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