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SLANJ (Intel Xeon X5260)

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SLANJ specifications

General information
TypeCPU / Microprocessor
FamilyIntel Xeon
Processor number  ? X5260
Part numberEU80573KJ0936M
Frequency (GHz)  ? 3.333
Bus speed (MHz)  ? 1333
Package type771-land FC-LGA8
Socket typeSocket 771 (LGA771)
 
Architecture / Microarchitecture / Other
CPUID10676h
Core steppingC0
Next steppingQFYN
Next production steppingSLBAS
Processor coreWolfdale
Manufacturing technology (micron)0.045
Number of cores2
L2 cache size (MB)  ? 6
FeaturesEM64T technology  ? 
Execute disable bit  ? 
Thermal Monitor 2
Virtualization technology
Core voltage (V)  ? 0.95 - 1.212
Case temperature (°C)  ? 66
Thermal Design Power (Watt)  ? 80
 
Notes on sSpec SLANJ
  • This part has Enhanced Halt State enabled.
  • The processor supports I/O Acceleration Technology.

Related S-Spec numbers

In addition to the SLANJ S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec AT80573KJ0936M EU80573KJ0936M
C0 Q624   +
SLANJ   +
E0 QFYN +  
SLBAS +  
Unknown Q4QY   +

NOTE: Engineering and qualifications samples are marked with this color


SLANJ CPUID information

Intel Xeon X5260 SLANJ
Part number:EU80573KJ0936M
Frequency:3333 MHz
Comment:HP WKS XW6600 dual cpu
Submitted by:Callahan [PL]
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Xeon(R) CPU X5260 @ 3.33GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:10676
Family: 6 (06h)
Model:23 (017h)
Stepping: 6 (06h)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 2 x 32 KB 2 x 32 KB 6 MB
Associativity: 8-way set
associative
8-way set
associative
24-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  Direct Cache access
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
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