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SLAPL (Intel Core 2 Duo E8400)

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SLAPL specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core 2 Duo
Processor number  ? E8400
Part numberEU80570PJ0806M
BX80570E8400
BXC80570E8400
BX80570E8400A
Frequency (GHz)  ? 3
Bus speed (MHz)  ? 1333
Clock multiplier  ? 9
Package type775-land FC-LGA8
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID010676h
Core steppingC0
Manufacturing technology (micron)0.045
Number of cores2
L2 cache size (MB)  ? 6
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Extended Stop Grant state
Thermal Monitor 2
Trusted Execution technology
Virtualization technology
Core voltage (V)  ? 0.85 - 1.3625
Case temperature (°C)  ? 72.4
Thermal Design Power (Watt)  ? 65
 
There are no notes on sSpec SLAPL

Related S-Spec numbers

In addition to the SLAPL S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec AT80570PJ0806M EU80570PJ0806M BX80570E8400 BX80570E8400A BXC80570E8400
C0 Q9HD   +      
SLAPL   + + + +
E0 QHEZ +        
QHGG +        
SLB9J +   +   +
Unknown Q5UE   +      
Q5UN   +      

NOTE: Engineering and qualifications samples are marked with this color


SLAPL CPUID information

Intel Core 2 Duo E8400 SLAPL
Part number:EU80570PJ0806M
Frequency:
Comment:
Submitted by:cocoe
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:10676
Family: 6 (06h)
Model:23 (017h)
Stepping: 6 (06h)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 32 KB 32 KB 6 MB
Associativity: 8-way set
associative
8-way set
associative
16-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Intel Trusted Execution technology Debug store
Enhanced SpeedStep Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

 

2012-08-20 11:10:22
Posted by: Homosapien

 

2012-08-20 11:11:07
Posted by: Homosapien

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