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SLAWE (Intel Core 2 Quad Q9300)

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SLAWE specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core 2 Quad
Processor number  ? Q9300
Part numberEU80580PJ0606M
BX80580Q9300
Frequency (GHz)  ? 2.5
Bus speed (MHz)  ? 1333
Clock multiplier  ? 7.5
Package type775-land FC-LGA8
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID010677h
Core steppingM1
Manufacturing technology (micron)0.045
Number of cores4
L2 cache size (MB)  ? 6
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Thermal Monitor 2
Trusted Execution technology
Virtualization technology
Core voltage (V)  ? 0.85 - 1.3625
Case temperature (°C)  ? 71.4
Thermal Design Power (Watt)  ? 95
 
Notes on sSpec SLAWE
  • The processor supports the 775_VR_CONFIG_05A (mainstream) guidelines for processors with TDP up to 95 Watt, Iccmax up to 100A, and VID up to 1.4V.

Related S-Spec numbers

In addition to the SLAWE S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec EU80580PJ0606M BX80580Q9300
B1 QAKY +  
M0 SLAMX +  
M1 SLAWE + +

NOTE: Engineering and qualifications samples are marked with this color


SLAWE CPUID information

Intel Core 2 Quad Q9300 SLAWE
Part number:EU80580PJ0606M
Frequency:3075 MHz
Comment:
Submitted by:Tim Oakes
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM)2 Quad CPU Q9300 @ 2.50GHz
Cores:4
Logical processors:4
Processor type:Original OEM Processor
CPUID signature:10677
Family: 6 (06h)
Model:23 (017h)
Stepping: 7 (07h)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 4 x 32 KB 4 x 32 KB 2 x 3 MB
Associativity: 8-way set
associative
8-way set
associative
12-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
1 cache per 2 cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
Intel Virtualization Advanced programmable interrupt controller
Intel Trusted Execution technology CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

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