SLAYY (Intel Core 2 Duo Mobile T9300)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Core 2 Duo Mobile |
| Processor number ? | T9300 |
| Part number | FF80576GG0606M BX80576T9300 |
| Frequency (GHz) | 2.5 |
| Frequency in IDA mode (GHz) | 2.7 |
| Frequency in LFM mode (GHz) | 1.2 |
| Frequency in SLFM mode (GHz) | 0.8 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 12.5 |
| Package type | 478-pin micro-FCPGA |
| Socket type | Socket P |
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| Architecture / Microarchitecture / Other |
| CPUID | 010676h |
| Core stepping | C0 |
| Processor core | Penryn |
| Manufacturing technology (micron) | 0.045 |
| Number of cores | 2 |
| L2 cache size (MB) ? | 6 |
| Features | EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Intel Dynamic Acceleration Virtualization technology |
| Core voltage (V) ? | 1 - 1.25 |
| Core voltage in IDA mode (V) | 1 - 1.3 |
| Core voltage in LFM mode (V) | 0.85 - 1.25 |
| Core voltage in SLFM mode (V) | 0.75 - 0.925 |
| Case temperature (°C) ? | 105 |
| Thermal Design Power (Watt) ? | 35 |
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| Notes on sSpec SLAYY |
- The part is discontinued. Last order date for OEM and boxed processors is July 24, 2009. Last shipment date for boxed processors is October 23, 2009. Last shipment date for OEM processors is September 24, 2010.
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CPU ID (1)
| Intel Core 2 Duo Mobile T9300 SLAYY |
| Part number: | FF80576GG0606M |
| Frequency: | |
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| Comment: | |
| Submitted by: | cocoe |
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| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10676 |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 6 (06h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
32 KB |
32 KB |
6 MB |
| Associativity: |
8-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
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| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Turbo Boost |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |