 |
News · Chips · Information · Forum · Links · About |
|---|---|
| Identification · Pinouts · S-Spec numbers · Glossary | |
SLB8V (Intel Core 2 Quad Q9550)
Specifications
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Core 2 Quad |
| Processor number ? | Q9550 |
| Part number | EU80569PJ073N BX80569Q9550 BXC80569Q9550 |
| Frequency (GHz) | 2.833 |
| Bus speed (MHz) ? | 1333 |
| Clock multiplier ? | 8.5 |
| Package type | 775-land FC-LGA8 |
| Socket type | Socket 775 (LGA775) |
| Architecture / Microarchitecture / Other | |
| CPUID | 01067Ah |
| Core stepping | E0 |
| Previous stepping | SLAWQ |
| Processor core | Yorkfield |
| Manufacturing technology (micron) | 0.045 |
| Number of cores | 4 |
| L2 cache size (MB) ? | 12 |
| Features | EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Extended Halt state Thermal Monitor 2 Trusted Execution technology Virtualization technology |
| Core voltage (V) ? | 0.85 - 1.3625 |
| Case temperature (°C) ? | 71.4 |
| Thermal Design Power (Watt) ? | 95 |
| Notes on sSpec SLB8V | |
| |
CPU ID (1)
| Intel Core 2 Quad Q9550 SLB8V | |||||||||
|---|---|---|---|---|---|---|---|---|---|
|
| ||||||||
| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Quad CPU Q9550 @ 2.83GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 1067A |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 10 (0Ah) |
| TLB/Cache details: | 64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 4 x 32 KB | 4 x 32 KB | 2 x 6 MB |
| Associativity: | 8-way set associative |
8-way set associative |
24-way set associative |
| Line size: | 64 bytes | 64 bytes | 64 bytes |
| Comments: | 1 cache per 2 cores |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG16B | ||
| SSE3 | CMPXCHG8B | ||
| SSSE3 | FXSAVE/FXRSTORE | ||
| SSE4.1 | MONITOR/MWAIT | ||
| SYSENTER/SYSEXIT | |||
| XSAVE/XRESTORE states | |||
| XSETBV/XGETBV are enabled | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit / Intel 64 | 64-bit debug store | ||
| Intel Virtualization | Advanced programmable interrupt controller | ||
| Intel Trusted Execution technology | CPL qualified debug store | ||
| Enhanced SpeedStep | Debug store | ||
| Debugging extensions | |||
| Digital Thermal Sensor capability | |||
| LAHF/SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor 2 | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
| Terms and Conditions · Privacy Policy · Contact Us | (c) Copyright 2003 - 2010 Gennadiy Shvets |
Search CPU-World
Identify part
Where to buy
Related S-Specs
Find Core 2 Quad S-Spec numbers with:
SLB8V vs SLAWQ
You have the steppings backwards. SLB6V is the E0 and the SLAWQ is C1
E0 is SLB8V
SLAWQ is C1 stepping.
Q9550-SLB8V
I can confirm it's stepping E0 in CPU-Z