SLB9T (Intel Pentium Dual-Core E5200)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Pentium Dual-Core |
| Processor number ? | E5200 |
| Part number | AT80571PG0602M BX80571E5200 BXC80571E5200 |
| Frequency (GHz) | 2.5 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 12.5 |
| Package type | 775-land FC-LGA8 |
| Socket type | Socket 775 (LGA775) |
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| Architecture / Microarchitecture / Other |
| CPUID | 01067Ah |
| Core stepping | R0 |
| Qualification sample | QJLU |
| Previous stepping | SLAY7 |
| Processor core | Wolfdale-3M |
| Manufacturing technology (micron) | 0.045 |
| Number of cores | 2 |
| L2 cache size (KB) ? | 2048 |
| Features | EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Extended Halt state Extended Stop Grant state Thermal Monitor 2 |
| Core voltage (V) ? | 0.85 - 1.3625 |
| Case temperature (°C) ? | 74.1 |
| Thermal Design Power (Watt) ? | 65 |
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| Notes on sSpec SLB9T |
- Deep Sleep low power mode is enabled.
- Deeper Sleep low power mode is enabled.
- OEM and boxed parts are available starting from April 13, 2009
- Changes in R0 stepping: Halide-free package, Added XSAVE/XRSTOR instructions, Power State Indicator support with Intel 4 series chipsets
- The part is discontinued. Last order date for OEM and boxed processors is May 7, 2010. Last shipment date for boxed processors is August 6, 2010. Last shipment date for OEM processors is January 7, 2011.
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CPU ID (1)
| Intel Pentium Dual-Core E5200 SLB9T |
| Part number: | EU80571PG0602M |
| Frequency: | 2500 MHz |
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| Comment: | |
| Submitted by: | vitrocmax |
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| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Pentium(R) Dual-Core CPU E5200 @ 2.50GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 1067A |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 10 (0Ah) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
2 x 32 KB |
2 x 32 KB |
2 MB |
| Associativity: |
8-way set associative |
8-way set associative |
8-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
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Shared between all cores |
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| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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XSAVE/XRESTORE states |
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XSETBV/XGETBV are enabled |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| Enhanced SpeedStep |
Advanced programmable interrupt controller |
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CPL qualified debug store |
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Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |