SLB9T (Intel Pentium Dual-Core E5200)


Specifications

General information
TypeCPU / Microprocessor
FamilyIntel Pentium Dual-Core
Processor number  ? E5200
Part numberAT80571PG0602M
BX80571E5200
BXC80571E5200
Frequency (GHz)2.5
Bus speed (MHz)  ? 800
Clock multiplier  ? 12.5
Package type775-land FC-LGA8
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID01067Ah
Core steppingR0
Qualification sampleQJLU
Previous steppingSLAY7
Processor coreWolfdale-3M
Manufacturing technology (micron)0.045
Number of cores2
L2 cache size (KB)  ? 2048
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Extended Stop Grant state
Thermal Monitor 2
Core voltage (V)  ? 0.85 - 1.3625
Case temperature (°C)  ? 74.1
Thermal Design Power (Watt)  ? 65
 
Notes on sSpec SLB9T
  • Deep Sleep low power mode is enabled.
  • Deeper Sleep low power mode is enabled.
  • OEM and boxed parts are available starting from April 13, 2009
  • Changes in R0 stepping: Halide-free package, Added XSAVE/XRSTOR instructions, Power State Indicator support with Intel 4 series chipsets
  • The part is discontinued. Last order date for OEM and boxed processors is May 7, 2010. Last shipment date for boxed processors is August 6, 2010. Last shipment date for OEM processors is January 7, 2011.
 

CPU ID (1)

Intel Pentium Dual-Core E5200 SLB9T
Part number:EU80571PG0602M
Frequency:2500 MHz
Comment:
Submitted by:vitrocmax
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Pentium(R) Dual-Core CPU E5200 @ 2.50GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:1067A
Family: 6 (06h)
Model:23 (017h)
Stepping:10 (0Ah)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 2 x 32 KB 2 x 32 KB 2 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments:     Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
  XSAVE/XRESTORE states
  XSETBV/XGETBV are enabled
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
Enhanced SpeedStep Advanced programmable interrupt controller
  CPL qualified debug store
  Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

Comments (0)

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