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SLBBA (Intel Xeon X5460)

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SLBBA specifications

General information
TypeCPU / Microprocessor
FamilyIntel Xeon
Processor number  ? X5460
Part numberAT80574KJ087N
BX80574X5460A
BX80574X5460P
Frequency (GHz)  ? 3.167
Bus speed (MHz)  ? 1333
Package type771-land FC-LGA
Socket typeSocket 771 (LGA771)
 
Architecture / Microarchitecture / Other
CPUID1067Ah
Core steppingE0
Qualification sampleQFTX
Previous steppingSLANP
Manufacturing technology (micron)0.045
Number of cores4
L2 cache size (MB)  ? 12
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Virtualization technology
Core voltage (V)  ? 1.212
Case temperature (°C)  ? 63
Thermal Design Power (Watt)  ? 120
 
Notes on sSpec SLBBA
  • OEM parts are available starting from Oct 6, 2008.
  • Boxed processors are available starting from Aug 29, 2008.
  • Changes in E0 stepping: new XSAVE and XRSTORE instructions, ACNT2 feature used for determining processor utilization, halide-free package.

Related S-Spec numbers

In addition to the SLBBA S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec AT80574KJ087N EU80574KJ087N BX80574X5460A BX80574X5460P
C0 Q5XQ   +    
SLANP   + + +
E0 QFTX +      
SLBBA +   + +

NOTE: Engineering and qualifications samples are marked with this color


SLBBA CPUID information

Intel Xeon X5460 SLBBA
Part number:EU80574KJ087N
Frequency:3610 MHz
Comment:
Submitted by:Shonk
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Xeon(R) CPU X5460 @ 3.16GHz
Cores:4
Logical processors:4
Processor type:Original OEM Processor
CPUID signature:1067A
Family: 6 (06h)
Model:23 (017h)
Stepping:10 (0Ah)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 4 x 32 KB 4 x 32 KB 2 x 6 MB
Associativity: 8-way set
associative
8-way set
associative
24-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
1 cache per 2 cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
  SYSENTER/SYSEXIT
  XSAVE/XRESTORE states
  XSETBV/XGETBV are enabled
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  Direct Cache access
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
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