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SLBV3 (Intel Xeon X5650)

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SLBV3 specifications

General information
TypeCPU / Microprocessor
FamilyIntel Xeon
Processor number  ? X5650
Part numberAT80614004320AD
BX80614X5650
Frequency (GHz)  ? 2.667
Bus speed (MHz)  ? 3200
Package type1366-land FC-LGA10
Socket typeSocket 1366 (LGA1366)
 
Architecture / Microarchitecture / Other
CPUID206C2h
Core steppingB1
Processor coreWestmere-EP
Manufacturing technology (micron)0.032
Number of cores6
L2 cache size (MB)  ? 1.5
L3 cache size (MB)12
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Hyper-Threading technology
Thermal Monitor 2
Turbo Boost technology
Virtualization technology
Core voltage (V)  ? 1.3
Case temperature (°C)  ? 81.3
Thermal Design Power (Watt)  ? 95
 
Notes on sSpec SLBV3
  • QuickPath Interconnect speed is 6.4 GT/s.
  • This part includes Turbo Boost Technology. Maximum performance increase in Turbo Boost mode is 266 MHz for 6, 5, 4 or 3 cores, and 400 MHz for 1 or 2 cores.
  • This part has Enhanced Halt State enabled.
  • The part supports DDR3-1333 memory.

Related S-Spec numbers

In addition to the SLBV3 S-Spec, this processor was also manufactured with a few pre-production S-Spec numbers:

SteppingS-Spec AT80614004320AD BX80614X5650
A0 Q3QN +  
B0 Q3UQ +  
B1 Q4EJ +  
SLBV3 + +

NOTE: Engineering and qualifications samples are marked with this color


SLBV3 CPUID information

Intel Xeon X5650 SLBV3
Part number:AT80614004320AD
Frequency:2660 MHz
Comment:
Submitted by:
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Xeon(R) CPU X5650 @ 2.67GHz
Cores:6
Logical processors:12
Processor type:Original OEM Processor
CPUID signature:206C2
Family: 6 (06h)
Model:44 (02Ch)
Stepping: 2 (02h)
TLB/Cache details:64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache: L1 data L1 instruction L2 L3
Size: 6 x 32 KB 6 x 32 KB 6 x 256 KB 12 MB
Associativity: 8-way set
associative
4-way set
associative
8-way set
associative
16-way set
associative
Line size: 64 bytes 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Inclusive
Direct-mapped
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
SSE4.2 PCLMULDQ
AES POPCNT
  RDTSCP
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 1 GB large page support
64-bit / Intel 64 36-bit page-size extensions
NX bit/XD-bit 64-bit debug store
Hyper-Threading Technology Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Intel Trusted Execution technology Debug store
Turbo Boost Debugging extensions
Enhanced SpeedStep Digital Thermal Sensor capability
  Direct Cache access
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Process context identifiers
  Self-snoop
  TSC rate is ensured to be invariant across all states
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

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