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SLBY2 (Intel Core i3-560)

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SLBY2 specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core i3
Processor number  ? i3-560
Part numberCM80616003177AH
BX80616I3560
BXC80616I3560
Frequency (GHz)  ? 3.333
Clock multiplier  ? 25
Package type1156-land FC-LGA10
Socket typeSocket 1156 (LGA1156)
 
Architecture / Microarchitecture / Other
CPUID020655h
Core steppingK0
Processor coreClarkdale
Manufacturing technology (micron)0.032
Number of cores2
L2 cache size (KB)  ? 512
L3 cache size (MB)4
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Hyper-Threading technology
Virtualization technology
Core voltage (V)  ? 0.65 - 1.4
Case temperature (°C)  ? 72.6
Thermal Design Power (Watt)  ? 73
 
Notes on sSpec SLBY2
  • Integrated graphics controller runs at 733 MHz.
  • The part supports DDR3-1333 memory.
  • The part is discontinued. Last order date for OEM and boxed processors is June 29, 2012. Last shipment date for OEM processors is December 7, 2012.

Related S-Spec numbers

In addition to the SLBY2 S-Spec, this processor was also manufactured with one pre-production S-Spec number:

SteppingS-Spec CM80616003177AH BX80616I3560 BXC80616I3560
K0 Q4P3 +    
SLBY2 + + +

NOTE: Engineering and qualifications samples are marked with this color


SLBY2 CPUID information

Intel Core i3 i3-560 SLBY2
Part number:CM80616003177AH
Frequency:3343 MHz
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM) i3 CPU 560 @ 3.33GHz
Cores:2
Logical processors:4
Processor type:Original OEM Processor
CPUID signature:20655
Family: 6 (06h)
Model:37 (025h)
Stepping: 5 (05h)
TLB/Cache details:64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache: L1 data L1 instruction L2 L3
Size: 2 x 32 KB 2 x 32 KB 2 x 256 KB 4 MB
Associativity: 8-way set
associative
4-way set
associative
8-way set
associative
16-way set
associative
Line size: 64 bytes 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Inclusive
Direct-mapped
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
SSE4.2 POPCNT
  RDTSCP
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Hyper-Threading Technology CPL qualified debug store
Intel Virtualization Debug store
Enhanced SpeedStep Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Process context identifiers
  Self-snoop
  TSC rate is ensured to be invariant across all states
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

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