SLG9S (Intel Core 2 Quad Q8200)

Specifications

General information
Type	CPU / Microprocessor
Family	Intel Core 2 Quad
Processor number ?	Q8200
Part number	AT80580PJ0534MN BX80580Q8200 BXC80580Q8200
Frequency (GHz)	2.333
Bus speed (MHz) ?	1333
Clock multiplier ?	7
Package type	775-land FC-LGA8
Socket type	Socket 775 (LGA775)

Architecture / Microarchitecture / Other
CPUID	01067Ah
Core stepping	R0
Qualification sample	QJLG
Previous stepping	SLB5M
Manufacturing technology (micron)	0.045
Number of cores	4
L2 cache size (MB) ?	4
Features	EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Extended Halt state Thermal Monitor 2
Core voltage (V) ?	0.85 - 1.3625
Case temperature (°C) ?	71.4
Thermal Design Power (Watt) ?	95

Notes on sSpec SLG9S
Deep Sleep low power mode is enabled. Deeper Sleep low power mode is enabled. OEM parts are available starting from February 23, 2009. Boxed processors are available starting from February 23, 2009. Changes in R0 stepping: Extended Stop Grant state, Deep Sleep state, Deeper Sleep state, support for Power Status Indicator signal, new XSAVE and XRSTORE instructions, halide-gree package. The part is discontinued. Last order date for OEM and boxed processors is May 7, 2010. Last shipment date for boxed processors is August 6, 2010. Last shipment date for OEM processors is July 8, 2011.

CPU ID (1)

View / search public CPUID submissions | Check your CPU

Intel Core 2 Quad Q8200 SLG9S

Part number:	EU80580PJ0534MN
Frequency:	2333 MHz

Comment:	One sweet quadcore
Submitted by:	David

General information
Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Core(TM)2 Quad CPU Q8200 @ 2.33GHz
Cores:	4
Logical processors:	4
Processor type:	Original OEM Processor
CPUID signature:	1067A
Family:	6 (06h)
Model:	23 (017h)
Stepping:	10 (0Ah)
TLB/Cache details:	64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2

Size: 4 x 32 KB 4 x 32 KB 2 x 2 MB

Associativity: 8-way set
associative 8-way set
associative 8-way set
associative

Line size: 64 bytes 64 bytes 64 bytes

Comments: 1 cache per 2 cores

Instruction set extensions Additional instructions

MMX CLFLUSH

SSE CMOV

SSE2 CMPXCHG16B

SSE3 CMPXCHG8B

SSSE3 FXSAVE/FXRSTORE

SSE4.1 MONITOR/MWAIT

SYSENTER/SYSEXIT

XSAVE/XRESTORE states

Major features Other features

On-chip Floating Point Unit 36-bit page-size extensions

64-bit / Intel 64 64-bit debug store

NX bit/XD-bit Advanced programmable interrupt controller

Enhanced SpeedStep CPL qualified debug store

Debug store

Debugging extensions

Digital Thermal Sensor capability

LAHF/SAHF support in 64-bit mode

Machine check architecture

Machine check exception

Memory-type range registers

Model-specific registers

Page attribute table

Page global extension

Page-size extensions (4MB pages)

Pending break enable

Perfmon and Debug capability

Physical address extensions

Self-snoop

Thermal monitor

Thermal monitor 2

Thermal monitor and software controlled clock facilities

Time stamp counter

Virtual 8086-mode enhancements

xTPR Update Control

Comments (1)