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SLGTL (Intel Pentium E5300)

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SLGTL specifications

General information
TypeCPU / Microprocessor
FamilyIntel Pentium Dual-Core
Processor number  ? E5300
Part numberAT80571PG0642ML
BX80571E5300
BXC80571E5300
Frequency (GHz)  ? 2.6
Bus speed (MHz)  ? 800
Clock multiplier  ? 13
Package type775-land FC-LGA8
Socket typeSocket 775 (LGA775)
 
Architecture / Microarchitecture / Other
CPUID01067Ah
Core steppingR0
Qualification sampleQLQG
Previous steppingSLB9U
Processor coreWolfdale-3M
Manufacturing technology (micron)0.045
Number of cores2
L2 cache size (MB)  ? 2
FeaturesEM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Extended Halt state
Extended Stop Grant state
Thermal Monitor 2
Virtualization technology
Core voltage (V)  ? 0.85 - 1.3625
Case temperature (°C)  ? 74.1
Thermal Design Power (Watt)  ? 65
 
Notes on sSpec SLGTL
  • Deep Sleep low power mode is enabled.
  • Deeper Sleep low power mode is enabled.
  • OEM parts are available starting from June 12, 2009.
  • Boxed parts are available starting from August 3, 2009.

Related S-Spec numbers

In addition to the SLGTL S-Spec, this processor was also manufactured with two production S-Spec numbers:

SteppingS-Spec AT80571PG0642M AT80571PG0642ML BX80571E5300 BXC80571E5300
R0 SLB9U +   + +
SLGQ6 +   + +
SLGTL   + + +

SLGTL CPUID information

Intel Pentium Dual-Core E5300 SLGTL
Part number:AT80571PG0642M
Frequency:4352 MHz
Comment:
Submitted by:
 
General information
Vendor:GenuineIntel
Processor name (BIOS):Pentium(R) Dual-Core CPU E5300 @ 2.60GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:1067A
Family: 6 (06h)
Model:23 (017h)
Stepping:10 (0Ah)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 2 x 32 KB 2 x 32 KB 2 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
  XSAVE / XRESTORE states
  XSETBV / XGETBV are enabled
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

Our CPUID database has 2 records for this microprocessor. See all submitted records.

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