Search CPU-World

Search site contents:

SR02N (Intel Core i7-2670QM)

Identify another S-Spec code, or another CPU:

The specs can be used for short-term listings on auction and classifieds sites:

Get HTML and forum link code in case if you want to link to this page:

Search S-Specs

Find Core i7 Mobile S-Spec numbers with:

Same socket
Same stepping

SR02N specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core i7 Mobile
Processor number  ? i7-2670QM
Part numberFF8062701065500
Frequency (GHz)  ? 2.2
Frequency in IDA mode (GHz)3.1
Clock multiplier  ? 22
Package type988-pin micro-FCPGA
Socket typeSocket G2 (rPGA988B)
 
Architecture / Microarchitecture / Other
Core steppingD2
Processor coreSandy Bridge
Manufacturing technology (micron)0.032
Number of cores4
L2 cache size (MB)  ? 1
L3 cache size (MB)6
FeaturesAES
AVX
EM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Hyper-Threading technology
MMX
SSE
SSE2
SSE3
SSE4
SSSE3
Turbo Boost technology
Virtualization technology (VT-x)
Case temperature (°C)  ? 100
Thermal Design Power (Watt)  ? 45
 
Notes on sSpec SR02N
  • The part supports DDR3-1066 and DDR3-1333 memory.
  • Direct Memory Interface speed is 5 GT/s.
  • Frequency of integrated graphics controller in turbo mode is 1100 MHz.
  • Integrated graphics controller runs at 650 MHz.

SR02N CPUID information

Intel Core i7 Mobile i7-2670QM SR02N
Part number:FF8062701065500
Frequency:2200 MHz
Comment:
Submitted by:CPU-World
 
General information
Vendor:GenuineIntel
Processor name (BIOS): Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz
Cores:4
Logical processors:8
Processor type:Original OEM Processor
CPUID signature:206A7
Family: 6 (06h)
Model:42 (02Ah)
Stepping: 7 (07h)
TLB/Cache details:64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
L2 TLB: 1-MB, 4-way set associative, 64-byte line size
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache: L1 data L1 instruction L2 L3
Size: 4 x 32 KB 4 x 32 KB 4 x 256 KB 6 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
12-way set
associative
Line size: 64 bytes 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Inclusive
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
SSE4.2 PCLMULDQ
AVX POPCNT
  RDTSCP
  SYSENTER/SYSEXIT
  XSAVE/XRESTORE states
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Hyper-Threading Technology CPL qualified debug store
Intel Virtualization Debug store
Turbo Boost Debugging extensions
Enhanced SpeedStep Digital Thermal Sensor capability
  Extended xAPIC support
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Power Limit Notification capability
  Process context identifiers
  Self-snoop
  TSC rate is ensured to be invariant across all states
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Timestamp counter deadline
  Virtual 8086-mode enhancements
  xTPR Update Control
Comments

Terms and Conditions · Privacy Policy · Contact Us (c) Copyright 2003 - 2010 Gennadiy Shvets