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SR0H9 (Intel Core i7-3930K)

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SR0H9 specifications

General information
TypeCPU / Microprocessor
FamilyIntel Core i7
Processor number  ? i7-3930K
Part numberCM8061901100802
BX80619I73930K
Frequency (GHz)  ? 3.2
Clock multiplier  ? 32
Package type2011-land FC-LGA10
Socket typeSocket 2011 (LGA2011)
 
Architecture / Microarchitecture / Other
Core steppingC1
Processor coreSandy Bridge-E
Manufacturing technology (micron)0.032
Number of cores6
L2 cache size (MB)  ? 1.5
L3 cache size (MB)12
FeaturesAES
AVX
EM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Hyper-Threading technology
Turbo Boost technology
Virtualization technology
Case temperature (°C)  ? 66.8
Thermal Design Power (Watt)  ? 130
 
Notes on sSpec SR0H9
  • The part supports DDR3-1066, DDR3-1333 and DDR3-1600 memory.
  • Direct Memory Interface speed is 5 GT/s.

Related S-Spec numbers

In addition to the SR0H9 S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

SteppingS-Spec CM8061901100802 BX80619I73930K
C0 QB7C +  
C1 QBF7 +  
SR0H9 + +
C2 QBV9 +  
SR0KY + +

NOTE: Engineering and qualifications samples are marked with this color


SR0H9 CPUID information

Intel Core i7 i7-3930K SR0H9
Part number:CM8061901100802
Frequency:3199 MHz
Comment:Stepping C1
Submitted by:debs3759
 
General information
Vendor:GenuineIntel
Processor name (BIOS): Intel(R) Core(TM) i7-3930K CPU @ 3.20GHz
Cores:6
Logical processors:12
Processor type:Original OEM Processor
CPUID signature:206D6
Family: 6 (06h)
Model:45 (02Dh)
Stepping: 6 (06h)
TLB/Cache details:64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
L2 TLB: 1-MB, 4-way set associative, 64-byte line size
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache: L1 data L1 instruction L2 L3
Size: 6 x 32 KB 6 x 32 KB 6 x 256 KB 12 MB
Associativity: 8-way set
associative
8-way set
associative
8-way set
associative
16-way set
associative
Line size: 64 bytes 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped
Inclusive
Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
SSE4.2 PCLMULDQ
AES POPCNT
AVX RDTSCP
  SYSENTER/SYSEXIT
  XSAVE / XRESTORE states
 
Major featuresOther features
On-chip Floating Point Unit 1 GB large page support
64-bit / Intel 64 36-bit page-size extensions
NX bit/XD-bit 64-bit debug store
Hyper-Threading Technology Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Turbo Boost Debug store
Enhanced SpeedStep Debugging extensions
  Digital Thermal Sensor capability
  Direct Cache access
  Extended xAPIC support
  LAHF / SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Power Limit Notification capability
  Process context identifiers
  Self-snoop
  TSC rate is ensured to be invariant across all states
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Timestamp counter deadline
  Virtual 8086-mode enhancements
  xTPR Update Control
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