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SR0P2 (Intel Core i5-3450S)
Specifications
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Core i5 |
| Processor number ? | i5-3450S |
| Part number | CM8063701095104 BX80637I53450S |
| Frequency (GHz) | 2.8 |
| Clock multiplier ? | 28 |
| Package type | 1155-land FC-LGA12C |
| Socket type | Socket 1155 (LGA1155) |
| Architecture / Microarchitecture / Other | |
| Core stepping | E1 |
| Processor core | Ivy Bridge |
| Manufacturing technology (micron) | 0.022 |
| Number of cores | 4 |
| L2 cache size (KB) ? | 1024 |
| L3 cache size (MB) | 6 |
| Features | EM64T technology ? Execute disable bit ? Turbo Boost technology Virtualization technology |
| Thermal Design Power (Watt) ? | 65 |
There are no notes on sSpec SR0P2 | |
CPU ID (1)
| Intel Core i5 i5-3450S SR0P2 | |||||||||
|---|---|---|---|---|---|---|---|---|---|
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| ||||||||
| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM) i5-3450S CPU @ 2.80GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 306A9 |
| Family: | 6 (06h) |
| Model: | 58 (03Ah) |
| Stepping: | 9 (09h) |
| TLB/Cache details: | 64-byte Prefetching Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries Data TLB: 4-KB Pages, 4-way set associative, 64 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L2 TLB: 1-MB, 4-way set associative, 64-byte line size Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: | L1 data | L1 instruction | L2 | L3 |
|---|---|---|---|---|
| Size: | 4 x 32 KB | 4 x 32 KB | 4 x 256 KB | 6 MB |
| Associativity: | 8-way set associative |
8-way set associative |
8-way set associative |
12-way set associative |
| Line size: | 64 bytes | 64 bytes | 64 bytes | 64 bytes |
| Comments: | Direct-mapped | Direct-mapped | Non-inclusive Direct-mapped |
Inclusive Shared between all cores |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG16B | ||
| SSE3 | CMPXCHG8B | ||
| SSSE3 | FXSAVE/FXRSTORE | ||
| SSE4.1 | MONITOR/MWAIT | ||
| SSE4.2 | PCLMULDQ | ||
| AES | POPCNT | ||
| AVX | RDRAND | ||
| F16C | RDTSCP | ||
| SYSENTER/SYSEXIT | |||
| XSAVE / XRESTORE states | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit / Intel 64 | 64-bit debug store | ||
| NX bit/XD-bit | Advanced programmable interrupt controller | ||
| Intel Virtualization | CPL qualified debug store | ||
| Turbo Boost | Debug store | ||
| Enhanced SpeedStep | Debugging extensions | ||
| Digital Thermal Sensor capability | |||
| LAHF / SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Power Limit Notification capability | |||
| Process context identifiers | |||
| Self-snoop | |||
| TSC rate is ensured to be invariant across all states | |||
| Thermal monitor | |||
| Thermal monitor 2 | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Timestamp counter deadline | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
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